Commit 0c1a94e2 authored by Stanislaw Gruszka's avatar Stanislaw Gruszka
Browse files

iwlegacy: rename i/o direct methods 



Signed-off-by: default avatarStanislaw Gruszka <sgruszka@redhat.com>
parent 1c8cae57

drivers/net/wireless/iwlegacy/iwl-3945.c

+15 −15
Original line number Diff line number Diff line
@@ -773,11 +773,11 @@ static void il3945_set_pwr_vmain(struct il_priv *il) 


static int il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)

{

	il_write_direct32(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);

	il_write_direct32(il, FH39_RCSR_RPTR_ADDR(0),

	il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);

	il_wr(il, FH39_RCSR_RPTR_ADDR(0),

					rxq->rb_stts_dma);

	il_write_direct32(il, FH39_RCSR_WPTR(0), 0);

	il_write_direct32(il, FH39_RCSR_CONFIG(0),

	il_wr(il, FH39_RCSR_WPTR(0), 0);

	il_wr(il, FH39_RCSR_CONFIG(0),

		FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |

		FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |

		FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
@@ -788,7 +788,7 @@ static int il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 
		FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);



	/* fake read to flush all prev I/O */

	il_read_direct32(il, FH39_RSSR_CTRL);

	il_rd(il, FH39_RSSR_CTRL);



	return 0;

}
@@ -810,10 +810,10 @@ static int il3945_tx_reset(struct il_priv *il) 
	il_write_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);

	il_write_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);



	il_write_direct32(il, FH39_TSSR_CBB_BASE,

	il_wr(il, FH39_TSSR_CBB_BASE,

			     il->_3945.shared_phys);



	il_write_direct32(il, FH39_TSSR_MSG_CONFIG,

	il_wr(il, FH39_TSSR_MSG_CONFIG,

		FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |

		FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |

		FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
@@ -987,7 +987,7 @@ int il3945_hw_nic_init(struct il_priv *il) 
	il_rx_queue_update_write_ptr(il, rxq);

	*/



	il_write_direct32(il, FH39_RCSR_WPTR(0), rxq->write & ~7);

	il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);



	rc = il3945_txq_ctx_reset(il);

	if (rc)
@@ -1030,8 +1030,8 @@ void il3945_hw_txq_ctx_stop(struct il_priv *il) 


	/* reset TFD queues */

	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {

		il_write_direct32(il, FH39_TCSR_CONFIG(txq_id), 0x0);

		il_poll_direct_bit(il, FH39_TSSR_TX_STATUS,

		il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);

		il_poll_bit(il, FH39_TSSR_TX_STATUS,

				FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),

				1000);

	}
@@ -2183,8 +2183,8 @@ int il3945_hw_rxq_stop(struct il_priv *il) 
{

	int rc;



	il_write_direct32(il, FH39_RCSR_CONFIG(0), 0);

	rc = il_poll_direct_bit(il, FH39_RSSR_STATUS,

	il_wr(il, FH39_RCSR_CONFIG(0), 0);

	rc = il_poll_bit(il, FH39_RSSR_STATUS,

			FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);

	if (rc < 0)

		IL_ERR("Can't stop Rx DMA.\n");
@@ -2200,10 +2200,10 @@ int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) 


	shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);



	il_write_direct32(il, FH39_CBCC_CTRL(txq_id), 0);

	il_write_direct32(il, FH39_CBCC_BASE(txq_id), 0);

	il_wr(il, FH39_CBCC_CTRL(txq_id), 0);

	il_wr(il, FH39_CBCC_BASE(txq_id), 0);



	il_write_direct32(il, FH39_TCSR_CONFIG(txq_id),

	il_wr(il, FH39_TCSR_CONFIG(txq_id),

		FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |

		FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |

		FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |

drivers/net/wireless/iwlegacy/iwl-4965-lib.c

+9 −9
Original line number Diff line number Diff line
@@ -103,17 +103,17 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 
		rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;



	/* Stop Rx DMA */

	il_write_direct32(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);

	il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);



	/* Reset driver's Rx queue write index */

	il_write_direct32(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);

	il_wr(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);



	/* Tell device where to find RBD circular buffer in DRAM */

	il_write_direct32(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG,

	il_wr(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG,

			   (u32)(rxq->bd_dma >> 8));



	/* Tell device where in DRAM to update its Rx status */

	il_write_direct32(il, FH_RSCSR_CHNL0_STTS_WPTR_REG,

	il_wr(il, FH_RSCSR_CHNL0_STTS_WPTR_REG,

			   rxq->rb_stts_dma >> 4);



	/* Enable Rx DMA
@@ -122,7 +122,7 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 
	 * RB timeout 0x10

	 * 256 RBDs

	 */

	il_write_direct32(il, FH_MEM_RCSR_CHNL0_CONFIG_REG,

	il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG,

			   FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |

			   FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |

			   FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
@@ -403,8 +403,8 @@ int il4965_rxq_stop(struct il_priv *il) 
{



	/* stop Rx DMA */

	il_write_direct32(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);

	il_poll_direct_bit(il, FH_MEM_RSSR_RX_STATUS_REG,

	il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);

	il_poll_bit(il, FH_MEM_RSSR_RX_STATUS_REG,

			    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);



	return 0;
@@ -1179,7 +1179,7 @@ int il4965_dump_fh(struct il_priv *il, char **buf, bool display) 
			pos += scnprintf(*buf + pos, bufsz - pos,

				"  %34s: 0X%08x\n",

				il4965_get_fh_string(fh_tbl[i]),

				il_read_direct32(il, fh_tbl[i]));

				il_rd(il, fh_tbl[i]));

		}

		return pos;

	}
@@ -1188,7 +1188,7 @@ int il4965_dump_fh(struct il_priv *il, char **buf, bool display) 
	for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {

		IL_ERR("  %34s: 0X%08x\n",

			il4965_get_fh_string(fh_tbl[i]),

			il_read_direct32(il, fh_tbl[i]));

			il_rd(il, fh_tbl[i]));

	}

	return 0;

}

drivers/net/wireless/iwlegacy/iwl-4965-tx.c

+5 −5
Original line number Diff line number Diff line
@@ -640,7 +640,7 @@ int il4965_txq_ctx_alloc(struct il_priv *il) 
	il4965_txq_set_sched(il, 0);



	/* Tell NIC where to find the "keep warm" buffer */

	il_write_direct32(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);

	il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);



	spin_unlock_irqrestore(&il->lock, flags);
@@ -679,7 +679,7 @@ void il4965_txq_ctx_reset(struct il_priv *il) 
	il4965_txq_set_sched(il, 0);



	/* Tell NIC where to find the "keep warm" buffer */

	il_write_direct32(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);

	il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);



	spin_unlock_irqrestore(&il->lock, flags);
@@ -707,14 +707,14 @@ void il4965_txq_ctx_stop(struct il_priv *il) 


	/* Stop each Tx DMA channel, and wait for it to be idle */

	for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {

		il_write_direct32(il,

		il_wr(il,

				FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);

		if (il_poll_direct_bit(il, FH_TSSR_TX_STATUS_REG,

		if (il_poll_bit(il, FH_TSSR_TX_STATUS_REG,

				    FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),

				    1000))

			IL_ERR("Failing on timeout while stopping"

			    " DMA channel %d [0x%08x]", ch,

			    il_read_direct32(il,

			    il_rd(il,

					FH_TSSR_TX_STATUS_REG));

	}

	spin_unlock_irqrestore(&il->lock, flags);

drivers/net/wireless/iwlegacy/iwl-4965-ucode.c

+2 −2
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ il4965_verify_inst_sparse(struct il_priv *il, __le32 *image, u32 len) 
		/* read data comes through single port, auto-incr addr */

		/* NOTE: Use the debugless read so we don't flood kernel log

		 * if IL_DL_IO is set */

		il_write_direct32(il, HBUS_TARG_MEM_RADDR,

		il_wr(il, HBUS_TARG_MEM_RADDR,

			i + IWL4965_RTC_INST_LOWER_BOUND);

		val = _il_rd(il, HBUS_TARG_MEM_RDAT);

		if (val != le32_to_cpu(*image)) {
@@ -89,7 +89,7 @@ static int il4965_verify_inst_full(struct il_priv *il, __le32 *image, 


	D_INFO("ucode inst image size is %u\n", len);



	il_write_direct32(il, HBUS_TARG_MEM_RADDR,

	il_wr(il, HBUS_TARG_MEM_RADDR,

			   IWL4965_RTC_INST_LOWER_BOUND);



	errcnt = 0;

drivers/net/wireless/iwlegacy/iwl-csr.h

+2 −2
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ 
 *

 * Use _il_wr() and _il_rd() family to access these registers;

 * these provide simple PCI bus access, without waking up the MAC.

 * Do not use il_write_direct32() family for these registers;

 * Do not use il_wr() family for these registers;

 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.

 * The MAC (uCode processor, etc.) does not need to be powered up for accessing

 * the CSR registers.
@@ -368,7 +368,7 @@ 
 * to indirectly access device's internal memory or registers that

 * may be powered-down.

 *

 * Use il_write_direct32()/il_read_direct32() family

 * Use il_wr()/il_rd() family

 * for these registers;

 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ

 * to make sure the MAC (uCode processor, etc.) is powered up for accessing