Commit f3de8530 authored by Pierre Gondois's avatar Pierre Gondois Committed by Krzysztof Kozlowski
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arm64: dts: exynos: Update cache properties 



The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: default avatarPierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221123092449.88097-2-pierre.gondois@arm.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 1b929c02

arch/arm64/boot/dts/exynos/exynos5433.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -226,6 +226,8 @@ cpu7: cpu@3 { 


		cluster_a57_l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;
@@ -233,6 +235,8 @@ cluster_a57_l2: l2-cache0 { 


		cluster_a53_l2: l2-cache1 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x40000>;

			cache-line-size = <64>;

			cache-sets = <256>;

arch/arm64/boot/dts/exynos/exynos7.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -107,6 +107,8 @@ cpu_atlas3: cpu@3 { 


		atlas_l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;