Commit 01158487 authored by Huacai Chen's avatar Huacai Chen
Browse files

LoongArch: Introduce hardware page table walker 



Loongson-3A6000 and newer processors have hardware page table walker
(PTW) support. PTW can handle all fastpaths of TLBI/TLBL/TLBS/TLBM
exceptions by hardware, software only need to handle slowpaths (page
faults).

BTW, PTW doesn't append _PAGE_MODIFIED for page table entries, so we
change pmd_dirty() and pte_dirty() to also check _PAGE_DIRTY for the
"dirty" attribute.

Signed-off-by: default avatarLiang Gao <gaoliang@loongson.cn>
Signed-off-by: default avatarJun Yi <yijun@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent e031a5f3

arch/loongarch/include/asm/cpu-features.h

+1 −1
Original line number Diff line number Diff line
@@ -64,6 +64,6 @@ 
#define cpu_has_eiodecode	cpu_opt(LOONGARCH_CPU_EIODECODE)

#define cpu_has_guestid		cpu_opt(LOONGARCH_CPU_GUESTID)

#define cpu_has_hypervisor	cpu_opt(LOONGARCH_CPU_HYPERVISOR)



#define cpu_has_ptw		cpu_opt(LOONGARCH_CPU_PTW)



#endif /* __ASM_CPU_FEATURES_H */

arch/loongarch/include/asm/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ enum cpu_type_enum { 
#define CPU_FEATURE_EIODECODE		23	/* CPU has EXTIOI interrupt pin decode mode */

#define CPU_FEATURE_GUESTID		24	/* CPU has GuestID feature */

#define CPU_FEATURE_HYPERVISOR		25	/* CPU has hypervisor (running in VM) */

#define CPU_FEATURE_PTW			26	/* CPU has hardware page table walker */



#define LOONGARCH_CPU_CPUCFG		BIT_ULL(CPU_FEATURE_CPUCFG)

#define LOONGARCH_CPU_LAM		BIT_ULL(CPU_FEATURE_LAM)
@@ -125,5 +126,6 @@ enum cpu_type_enum { 
#define LOONGARCH_CPU_EIODECODE		BIT_ULL(CPU_FEATURE_EIODECODE)

#define LOONGARCH_CPU_GUESTID		BIT_ULL(CPU_FEATURE_GUESTID)

#define LOONGARCH_CPU_HYPERVISOR	BIT_ULL(CPU_FEATURE_HYPERVISOR)

#define LOONGARCH_CPU_PTW		BIT_ULL(CPU_FEATURE_PTW)



#endif /* _ASM_CPU_H */

arch/loongarch/include/asm/loongarch.h

+4 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ __asm__(".macro parse_r var r\n\t" 
#define  CPUCFG2_MIPSBT			BIT(20)

#define  CPUCFG2_LSPW			BIT(21)

#define  CPUCFG2_LAM			BIT(22)

#define  CPUCFG2_PTW			BIT(24)



#define LOONGARCH_CPUCFG3		0x3

#define  CPUCFG3_CCDMA			BIT(0)
@@ -412,6 +413,9 @@ __asm__(".macro parse_r var r\n\t" 
#define  CSR_PWCTL0_PTBASE		(_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT)



#define LOONGARCH_CSR_PWCTL1		0x1d	/* PWCtl1 */

#define  CSR_PWCTL1_PTW_SHIFT		24

#define  CSR_PWCTL1_PTW_WIDTH		1

#define  CSR_PWCTL1_PTW			(_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT)

#define  CSR_PWCTL1_DIR3WIDTH_SHIFT	18

#define  CSR_PWCTL1_DIR3WIDTH_WIDTH	5

#define  CSR_PWCTL1_DIR3WIDTH		(_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT)

arch/loongarch/include/asm/pgtable.h

+2 −2
Original line number Diff line number Diff line
@@ -362,7 +362,7 @@ extern pgd_t invalid_pg_dir[]; 
 */

static inline int pte_write(pte_t pte)	{ return pte_val(pte) & _PAGE_WRITE; }

static inline int pte_young(pte_t pte)	{ return pte_val(pte) & _PAGE_ACCESSED; }

static inline int pte_dirty(pte_t pte)	{ return pte_val(pte) & _PAGE_MODIFIED; }

static inline int pte_dirty(pte_t pte)	{ return pte_val(pte) & (_PAGE_DIRTY | _PAGE_MODIFIED); }



static inline pte_t pte_mkold(pte_t pte)

{
@@ -506,7 +506,7 @@ static inline pmd_t pmd_wrprotect(pmd_t pmd) 


static inline int pmd_dirty(pmd_t pmd)

{

	return !!(pmd_val(pmd) & _PAGE_MODIFIED);

	return !!(pmd_val(pmd) & (_PAGE_DIRTY | _PAGE_MODIFIED));

}



static inline pmd_t pmd_mkclean(pmd_t pmd)

arch/loongarch/include/asm/tlb.h

+3 −0
Original line number Diff line number Diff line
@@ -158,6 +158,9 @@ extern void handle_tlb_store(void); 
extern void handle_tlb_modify(void);

extern void handle_tlb_refill(void);

extern void handle_tlb_protect(void);

extern void handle_tlb_load_ptw(void);

extern void handle_tlb_store_ptw(void);

extern void handle_tlb_modify_ptw(void);



extern void dump_tlb_all(void);

extern void dump_tlb_regs(void);