Commit 01a09255 authored by Eduard Zingerman's avatar Eduard Zingerman Committed by Alexei Starovoitov
Browse files

selftests/bpf: verifier/div0.c converted to inline assembly 



Test verifier/div0.c automatically converted to use inline assembly.

Signed-off-by: default avatarEduard Zingerman <eddyz87@gmail.com>
Link: https://lore.kernel.org/r/20230325025524.144043-19-eddyz87@gmail.com


Signed-off-by: default avatarAlexei Starovoitov <ast@kernel.org>
parent 84988478

tools/testing/selftests/bpf/prog_tests/verifier.c

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include "verifier_const_or.skel.h"

#include "verifier_ctx_sk_msg.skel.h"

#include "verifier_direct_stack_access_wraparound.skel.h"

#include "verifier_div0.skel.h"



__maybe_unused

static void run_tests_aux(const char *skel_name, skel_elf_bytes_fn elf_bytes_factory)
@@ -52,3 +53,4 @@ void test_verifier_cgroup_storage(void) { RUN(verifier_cgroup_storage); } 
void test_verifier_const_or(void)             { RUN(verifier_const_or); }

void test_verifier_ctx_sk_msg(void)           { RUN(verifier_ctx_sk_msg); }

void test_verifier_direct_stack_access_wraparound(void) { RUN(verifier_direct_stack_access_wraparound); }

void test_verifier_div0(void)                 { RUN(verifier_div0); }

tools/testing/selftests/bpf/progs/verifier_div0.c

0 → 100644
+213 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Converted from tools/testing/selftests/bpf/verifier/div0.c */



#include <linux/bpf.h>

#include <bpf/bpf_helpers.h>

#include "bpf_misc.h"



SEC("socket")

__description("DIV32 by 0, zero check 1")

__success __success_unpriv __retval(42)

__naked void by_0_zero_check_1_1(void)

{

	asm volatile ("					\

	w0 = 42;					\

	w1 = 0;						\

	w2 = 1;						\

	w2 /= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("socket")

__description("DIV32 by 0, zero check 2")

__success __success_unpriv __retval(42)

__naked void by_0_zero_check_2_1(void)

{

	asm volatile ("					\

	w0 = 42;					\

	r1 = 0xffffffff00000000LL ll;			\

	w2 = 1;						\

	w2 /= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("socket")

__description("DIV64 by 0, zero check")

__success __success_unpriv __retval(42)

__naked void div64_by_0_zero_check(void)

{

	asm volatile ("					\

	w0 = 42;					\

	w1 = 0;						\

	w2 = 1;						\

	r2 /= r1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("socket")

__description("MOD32 by 0, zero check 1")

__success __success_unpriv __retval(42)

__naked void by_0_zero_check_1_2(void)

{

	asm volatile ("					\

	w0 = 42;					\

	w1 = 0;						\

	w2 = 1;						\

	w2 %%= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("socket")

__description("MOD32 by 0, zero check 2")

__success __success_unpriv __retval(42)

__naked void by_0_zero_check_2_2(void)

{

	asm volatile ("					\

	w0 = 42;					\

	r1 = 0xffffffff00000000LL ll;			\

	w2 = 1;						\

	w2 %%= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("socket")

__description("MOD64 by 0, zero check")

__success __success_unpriv __retval(42)

__naked void mod64_by_0_zero_check(void)

{

	asm volatile ("					\

	w0 = 42;					\

	w1 = 0;						\

	w2 = 1;						\

	r2 %%= r1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("DIV32 by 0, zero check ok, cls")

__success __retval(8)

__naked void _0_zero_check_ok_cls_1(void)

{

	asm volatile ("					\

	w0 = 42;					\

	w1 = 2;						\

	w2 = 16;					\

	w2 /= w1;					\

	r0 = r2;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("DIV32 by 0, zero check 1, cls")

__success __retval(0)

__naked void _0_zero_check_1_cls_1(void)

{

	asm volatile ("					\

	w1 = 0;						\

	w0 = 1;						\

	w0 /= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("DIV32 by 0, zero check 2, cls")

__success __retval(0)

__naked void _0_zero_check_2_cls_1(void)

{

	asm volatile ("					\

	r1 = 0xffffffff00000000LL ll;			\

	w0 = 1;						\

	w0 /= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("DIV64 by 0, zero check, cls")

__success __retval(0)

__naked void by_0_zero_check_cls(void)

{

	asm volatile ("					\

	w1 = 0;						\

	w0 = 1;						\

	r0 /= r1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("MOD32 by 0, zero check ok, cls")

__success __retval(2)

__naked void _0_zero_check_ok_cls_2(void)

{

	asm volatile ("					\

	w0 = 42;					\

	w1 = 3;						\

	w2 = 5;						\

	w2 %%= w1;					\

	r0 = r2;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("MOD32 by 0, zero check 1, cls")

__success __retval(1)

__naked void _0_zero_check_1_cls_2(void)

{

	asm volatile ("					\

	w1 = 0;						\

	w0 = 1;						\

	w0 %%= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("MOD32 by 0, zero check 2, cls")

__success __retval(1)

__naked void _0_zero_check_2_cls_2(void)

{

	asm volatile ("					\

	r1 = 0xffffffff00000000LL ll;			\

	w0 = 1;						\

	w0 %%= w1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("MOD64 by 0, zero check 1, cls")

__success __retval(2)

__naked void _0_zero_check_1_cls_3(void)

{

	asm volatile ("					\

	w1 = 0;						\

	w0 = 2;						\

	r0 %%= r1;					\

	exit;						\

"	::: __clobber_all);

}



SEC("tc")

__description("MOD64 by 0, zero check 2, cls")

__success __retval(-1)

__naked void _0_zero_check_2_cls_3(void)

{

	asm volatile ("					\

	w1 = 0;						\

	w0 = -1;					\

	r0 %%= r1;					\

	exit;						\

"	::: __clobber_all);

}



char _license[] SEC("license") = "GPL";

tools/testing/selftests/bpf/verifier/div0.c

deleted100644 → 0
+0 −184
Original line number Diff line number Diff line 
{

	"DIV32 by 0, zero check 1",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_2, 1),

	BPF_ALU32_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.result = ACCEPT,

	.retval = 42,

},

{

	"DIV32 by 0, zero check 2",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),

	BPF_MOV32_IMM(BPF_REG_2, 1),

	BPF_ALU32_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.result = ACCEPT,

	.retval = 42,

},

{

	"DIV64 by 0, zero check",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_2, 1),

	BPF_ALU64_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.result = ACCEPT,

	.retval = 42,

},

{

	"MOD32 by 0, zero check 1",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_2, 1),

	BPF_ALU32_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.result = ACCEPT,

	.retval = 42,

},

{

	"MOD32 by 0, zero check 2",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),

	BPF_MOV32_IMM(BPF_REG_2, 1),

	BPF_ALU32_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.result = ACCEPT,

	.retval = 42,

},

{

	"MOD64 by 0, zero check",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_2, 1),

	BPF_ALU64_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.result = ACCEPT,

	.retval = 42,

},

{

	"DIV32 by 0, zero check ok, cls",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_MOV32_IMM(BPF_REG_1, 2),

	BPF_MOV32_IMM(BPF_REG_2, 16),

	BPF_ALU32_REG(BPF_DIV, BPF_REG_2, BPF_REG_1),

	BPF_MOV64_REG(BPF_REG_0, BPF_REG_2),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 8,

},

{

	"DIV32 by 0, zero check 1, cls",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_0, 1),

	BPF_ALU32_REG(BPF_DIV, BPF_REG_0, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

{

	"DIV32 by 0, zero check 2, cls",

	.insns = {

	BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),

	BPF_MOV32_IMM(BPF_REG_0, 1),

	BPF_ALU32_REG(BPF_DIV, BPF_REG_0, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

{

	"DIV64 by 0, zero check, cls",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_0, 1),

	BPF_ALU64_REG(BPF_DIV, BPF_REG_0, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 0,

},

{

	"MOD32 by 0, zero check ok, cls",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_0, 42),

	BPF_MOV32_IMM(BPF_REG_1, 3),

	BPF_MOV32_IMM(BPF_REG_2, 5),

	BPF_ALU32_REG(BPF_MOD, BPF_REG_2, BPF_REG_1),

	BPF_MOV64_REG(BPF_REG_0, BPF_REG_2),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 2,

},

{

	"MOD32 by 0, zero check 1, cls",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_0, 1),

	BPF_ALU32_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 1,

},

{

	"MOD32 by 0, zero check 2, cls",

	.insns = {

	BPF_LD_IMM64(BPF_REG_1, 0xffffffff00000000LL),

	BPF_MOV32_IMM(BPF_REG_0, 1),

	BPF_ALU32_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 1,

},

{

	"MOD64 by 0, zero check 1, cls",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_0, 2),

	BPF_ALU64_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = 2,

},

{

	"MOD64 by 0, zero check 2, cls",

	.insns = {

	BPF_MOV32_IMM(BPF_REG_1, 0),

	BPF_MOV32_IMM(BPF_REG_0, -1),

	BPF_ALU64_REG(BPF_MOD, BPF_REG_0, BPF_REG_1),

	BPF_EXIT_INSN(),

	},

	.prog_type = BPF_PROG_TYPE_SCHED_CLS,

	.result = ACCEPT,

	.retval = -1,

},