Commit 01d9ccf8 authored by Oded Gabbay's avatar Oded Gabbay
Browse files

habanalabs/gaudi2: add asic registers header files 



Add the relevant GAUDI2 ASIC registers header files. These files are
generated automatically from a tool maintained by the VLSI engineers.

There are more files which are not upstreamed because only very few
defines from those files are used in the driver. For those files, I
copied the relevant defines into gaudi2_regs.h and gaudi2_masks.h, to
reduce the size of this patch.

Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent ccf991e4

drivers/misc/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h

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/* SPDX-License-Identifier: GPL-2.0

 *

 * Copyright (C) 2020 HabanaLabs Ltd.

 * All Rights Reserved.

 */



#ifndef __GAUDI2_ARC_COMMON_PACKETS_H__

#define __GAUDI2_ARC_COMMON_PACKETS_H__



/*

 * CPU IDs for each ARC CPUs

 */



#define CPU_ID_SCHED_ARC0		0	/* FARM_ARC0 */

#define CPU_ID_SCHED_ARC1		1	/* FARM_ARC1 */

#define CPU_ID_SCHED_ARC2		2	/* FARM_ARC2 */

#define CPU_ID_SCHED_ARC3		3	/* FARM_ARC3 */

/* Dcore1 MME Engine ARC instance used as scheduler */

#define CPU_ID_SCHED_ARC4		4	/* DCORE1_MME0 */

/* Dcore3 MME Engine ARC instance used as scheduler */

#define CPU_ID_SCHED_ARC5		5	/* DCORE3_MME0 */



#define CPU_ID_TPC_QMAN_ARC0		6	/* DCORE0_TPC0 */

#define CPU_ID_TPC_QMAN_ARC1		7	/* DCORE0_TPC1 */

#define CPU_ID_TPC_QMAN_ARC2		8	/* DCORE0_TPC2 */

#define CPU_ID_TPC_QMAN_ARC3		9	/* DCORE0_TPC3 */

#define CPU_ID_TPC_QMAN_ARC4		10	/* DCORE0_TPC4 */

#define CPU_ID_TPC_QMAN_ARC5		11	/* DCORE0_TPC5 */

#define CPU_ID_TPC_QMAN_ARC6		12	/* DCORE1_TPC0 */

#define CPU_ID_TPC_QMAN_ARC7		13	/* DCORE1_TPC1 */

#define CPU_ID_TPC_QMAN_ARC8		14	/* DCORE1_TPC2 */

#define CPU_ID_TPC_QMAN_ARC9		15	/* DCORE1_TPC3 */

#define CPU_ID_TPC_QMAN_ARC10		16	/* DCORE1_TPC4 */

#define CPU_ID_TPC_QMAN_ARC11		17	/* DCORE1_TPC5 */

#define CPU_ID_TPC_QMAN_ARC12		18	/* DCORE2_TPC0 */

#define CPU_ID_TPC_QMAN_ARC13		19	/* DCORE2_TPC1 */

#define CPU_ID_TPC_QMAN_ARC14		20	/* DCORE2_TPC2 */

#define CPU_ID_TPC_QMAN_ARC15		21	/* DCORE2_TPC3 */

#define CPU_ID_TPC_QMAN_ARC16		22	/* DCORE2_TPC4 */

#define CPU_ID_TPC_QMAN_ARC17		23	/* DCORE2_TPC5 */

#define CPU_ID_TPC_QMAN_ARC18		24	/* DCORE3_TPC0 */

#define CPU_ID_TPC_QMAN_ARC19		25	/* DCORE3_TPC1 */

#define CPU_ID_TPC_QMAN_ARC20		26	/* DCORE3_TPC2 */

#define CPU_ID_TPC_QMAN_ARC21		27	/* DCORE3_TPC3 */

#define CPU_ID_TPC_QMAN_ARC22		28	/* DCORE3_TPC4 */

#define CPU_ID_TPC_QMAN_ARC23		29	/* DCORE3_TPC5 */

#define CPU_ID_TPC_QMAN_ARC24		30	/* DCORE0_TPC6 - Never present */



#define CPU_ID_MME_QMAN_ARC0		31	/* DCORE0_MME0 */

#define CPU_ID_MME_QMAN_ARC1		32	/* DCORE2_MME0 */



#define CPU_ID_EDMA_QMAN_ARC0		33	/* DCORE0_EDMA0 */

#define CPU_ID_EDMA_QMAN_ARC1		34	/* DCORE0_EDMA1 */

#define CPU_ID_EDMA_QMAN_ARC2		35	/* DCORE1_EDMA0 */

#define CPU_ID_EDMA_QMAN_ARC3		36	/* DCORE1_EDMA1 */

#define CPU_ID_EDMA_QMAN_ARC4		37	/* DCORE2_EDMA0 */

#define CPU_ID_EDMA_QMAN_ARC5		38	/* DCORE2_EDMA1 */

#define CPU_ID_EDMA_QMAN_ARC6		39	/* DCORE3_EDMA0 */

#define CPU_ID_EDMA_QMAN_ARC7		40	/* DCORE3_EDMA1 */



#define CPU_ID_PDMA_QMAN_ARC0		41	/* DCORE0_PDMA0 */

#define CPU_ID_PDMA_QMAN_ARC1		42	/* DCORE0_PDMA1 */



#define CPU_ID_ROT_QMAN_ARC0		43	/* ROT0 */

#define CPU_ID_ROT_QMAN_ARC1		44	/* ROT1 */



#define CPU_ID_NIC_QMAN_ARC0		45	/* NIC0_0 */

#define CPU_ID_NIC_QMAN_ARC1		46	/* NIC0_1 */

#define CPU_ID_NIC_QMAN_ARC2		47	/* NIC1_0 */

#define CPU_ID_NIC_QMAN_ARC3		48	/* NIC1_1 */

#define CPU_ID_NIC_QMAN_ARC4		49	/* NIC2_0 */

#define CPU_ID_NIC_QMAN_ARC5		50	/* NIC2_1 */

#define CPU_ID_NIC_QMAN_ARC6		51	/* NIC3_0 */

#define CPU_ID_NIC_QMAN_ARC7		52	/* NIC3_1 */

#define CPU_ID_NIC_QMAN_ARC8		53	/* NIC4_0 */

#define CPU_ID_NIC_QMAN_ARC9		54	/* NIC4_1 */

#define CPU_ID_NIC_QMAN_ARC10		55	/* NIC5_0 */

#define CPU_ID_NIC_QMAN_ARC11		56	/* NIC5_1 */

#define CPU_ID_NIC_QMAN_ARC12		57	/* NIC6_0 */

#define CPU_ID_NIC_QMAN_ARC13		58	/* NIC6_1 */

#define CPU_ID_NIC_QMAN_ARC14		59	/* NIC7_0 */

#define CPU_ID_NIC_QMAN_ARC15		60	/* NIC7_1 */

#define CPU_ID_NIC_QMAN_ARC16		61	/* NIC8_0 */

#define CPU_ID_NIC_QMAN_ARC17		62	/* NIC8_1 */

#define CPU_ID_NIC_QMAN_ARC18		63	/* NIC9_0 */

#define CPU_ID_NIC_QMAN_ARC19		64	/* NIC9_1 */

#define CPU_ID_NIC_QMAN_ARC20		65	/* NIC10_0 */

#define CPU_ID_NIC_QMAN_ARC21		66	/* NIC10_1 */

#define CPU_ID_NIC_QMAN_ARC22		67	/* NIC11_0 */

#define CPU_ID_NIC_QMAN_ARC23		68	/* NIC11_1 */



#define CPU_ID_MAX			69

#define CPU_ID_SCHED_MAX		6



#define CPU_ID_ALL			0xFE

#define CPU_ID_INVALID			0xFF



enum arc_regions_t {

	ARC_REGION0_UNSED  = 0,

	/*

	 * Extension registers

	 * None

	 */

	ARC_REGION1_SRAM = 1,

	/*

	 * Extension registers

	 * AUX_SRAM_LSB_ADDR

	 * AUX_SRAM_MSB_ADDR

	 * ARC Address: 0x1000_0000

	 */

	ARC_REGION2_CFG = 2,

	/*

	 * Extension registers

	 * AUX_CFG_LSB_ADDR

	 * AUX_CFG_MSB_ADDR

	 * ARC Address: 0x2000_0000

	 */

	ARC_REGION3_GENERAL = 3,

	/*

	 * Extension registers

	 * AUX_GENERAL_PURPOSE_LSB_ADDR_0

	 * AUX_GENERAL_PURPOSE_MSB_ADDR_0

	 * ARC Address: 0x3000_0000

	 */

	ARC_REGION4_HBM0_FW = 4,

	/*

	 * Extension registers

	 * AUX_HBM0_LSB_ADDR

	 * AUX_HBM0_MSB_ADDR

	 * AUX_HBM0_OFFSET

	 * ARC Address: 0x4000_0000

	 */

	ARC_REGION5_HBM1_GC_DATA = 5,

	/*

	 * Extension registers

	 * AUX_HBM1_LSB_ADDR

	 * AUX_HBM1_MSB_ADDR

	 * AUX_HBM1_OFFSET

	 * ARC Address: 0x5000_0000

	 */

	ARC_REGION6_HBM2_GC_DATA = 6,

	/*

	 * Extension registers

	 * AUX_HBM2_LSB_ADDR

	 * AUX_HBM2_MSB_ADDR

	 * AUX_HBM2_OFFSET

	 * ARC Address: 0x6000_0000

	 */

	ARC_REGION7_HBM3_GC_DATA = 7,

	/*

	 * Extension registers

	 * AUX_HBM3_LSB_ADDR

	 * AUX_HBM3_MSB_ADDR

	 * AUX_HBM3_OFFSET

	 * ARC Address: 0x7000_0000

	 */

	ARC_REGION8_DCCM = 8,

	/*

	 * Extension registers

	 * None

	 * ARC Address: 0x8000_0000

	 */

	ARC_REGION9_PCIE = 9,

	/*

	 * Extension registers

	 * AUX_PCIE_LSB_ADDR

	 * AUX_PCIE_MSB_ADDR

	 * ARC Address: 0x9000_0000

	 */

	ARC_REGION10_GENERAL = 10,

	/*

	 * Extension registers

	 * AUX_GENERAL_PURPOSE_LSB_ADDR_1

	 * AUX_GENERAL_PURPOSE_MSB_ADDR_1

	 * ARC Address: 0xA000_0000

	 */

	ARC_REGION11_GENERAL = 11,

	/*

	 * Extension registers

	 * AUX_GENERAL_PURPOSE_LSB_ADDR_2

	 * AUX_GENERAL_PURPOSE_MSB_ADDR_2

	 * ARC Address: 0xB000_0000

	 */

	ARC_REGION12_GENERAL = 12,

	/*

	 * Extension registers

	 * AUX_GENERAL_PURPOSE_LSB_ADDR_3

	 * AUX_GENERAL_PURPOSE_MSB_ADDR_3

	 * ARC Address: 0xC000_0000

	 */

	ARC_REGION13_GENERAL = 13,

	/*

	 * Extension registers

	 * AUX_GENERAL_PURPOSE_LSB_ADDR_4

	 * AUX_GENERAL_PURPOSE_MSB_ADDR_4

	 * ARC Address: 0xD000_0000

	 */

	ARC_REGION14_GENERAL = 14,

	/*

	 * Extension registers

	 * AUX_GENERAL_PURPOSE_LSB_ADDR_5

	 * AUX_GENERAL_PURPOSE_MSB_ADDR_5

	 * ARC Address: 0xE000_0000

	 */

	ARC_REGION15_LBU = 15

	/*

	 * Extension registers

	 * None

	 * ARC Address: 0xF000_0000

	 */

};



#endif /* __GAUDI2_ARC_COMMON_PACKETS_H__ */

drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h

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/* SPDX-License-Identifier: GPL-2.0

 *

 * Copyright 2016-2020 HabanaLabs, Ltd.

 * All Rights Reserved.

 *

 */



/************************************

 ** This is an auto-generated file **

 **       DO NOT EDIT BELOW        **

 ************************************/



#ifndef ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_

#define ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_



/*

 *****************************************

 *   ARC_FARM_ARC0_ACP_ENG

 *   (Prototype: ARC_ACP_ENG)

 *****************************************

 */



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0 0x4E8F000



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_1 0x4E8F004



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_2 0x4E8F008



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_3 0x4E8F00C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_4 0x4E8F010



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_5 0x4E8F014



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_6 0x4E8F018



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_7 0x4E8F01C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_8 0x4E8F020



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_9 0x4E8F024



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_10 0x4E8F028



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_11 0x4E8F02C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_12 0x4E8F030



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_13 0x4E8F034



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_14 0x4E8F038



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_15 0x4E8F03C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_16 0x4E8F040



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_17 0x4E8F044



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_18 0x4E8F048



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_19 0x4E8F04C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_20 0x4E8F050



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_21 0x4E8F054



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_22 0x4E8F058



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_23 0x4E8F05C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_24 0x4E8F060



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_25 0x4E8F064



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_26 0x4E8F068



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_27 0x4E8F06C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_28 0x4E8F070



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_29 0x4E8F074



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_30 0x4E8F078



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_31 0x4E8F07C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_32 0x4E8F080



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_33 0x4E8F084



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_34 0x4E8F088



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_35 0x4E8F08C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_36 0x4E8F090



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_37 0x4E8F094



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_38 0x4E8F098



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_39 0x4E8F09C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_40 0x4E8F0A0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_41 0x4E8F0A4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_42 0x4E8F0A8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_43 0x4E8F0AC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_44 0x4E8F0B0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_45 0x4E8F0B4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_46 0x4E8F0B8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_47 0x4E8F0BC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_48 0x4E8F0C0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_49 0x4E8F0C4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_50 0x4E8F0C8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_51 0x4E8F0CC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_52 0x4E8F0D0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_53 0x4E8F0D4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_54 0x4E8F0D8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_55 0x4E8F0DC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_56 0x4E8F0E0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_57 0x4E8F0E4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_58 0x4E8F0E8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_59 0x4E8F0EC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_60 0x4E8F0F0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_61 0x4E8F0F4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_62 0x4E8F0F8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_63 0x4E8F0FC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_0 0x4E8F100



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_1 0x4E8F104



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_2 0x4E8F108



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_3 0x4E8F10C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_4 0x4E8F110



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_5 0x4E8F114



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_6 0x4E8F118



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_7 0x4E8F11C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_8 0x4E8F120



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_9 0x4E8F124



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_10 0x4E8F128



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_11 0x4E8F12C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_12 0x4E8F130



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_13 0x4E8F134



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_14 0x4E8F138



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_15 0x4E8F13C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_16 0x4E8F140



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_17 0x4E8F144



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_18 0x4E8F148



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_19 0x4E8F14C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_20 0x4E8F150



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_21 0x4E8F154



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_22 0x4E8F158



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_23 0x4E8F15C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_24 0x4E8F160



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_25 0x4E8F164



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_26 0x4E8F168



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_27 0x4E8F16C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_28 0x4E8F170



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_29 0x4E8F174



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_30 0x4E8F178



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_31 0x4E8F17C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_32 0x4E8F180



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_33 0x4E8F184



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_34 0x4E8F188



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_35 0x4E8F18C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_36 0x4E8F190



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_37 0x4E8F194



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_38 0x4E8F198



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_39 0x4E8F19C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_40 0x4E8F1A0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_41 0x4E8F1A4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_42 0x4E8F1A8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_43 0x4E8F1AC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_44 0x4E8F1B0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_45 0x4E8F1B4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_46 0x4E8F1B8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_47 0x4E8F1BC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_48 0x4E8F1C0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_49 0x4E8F1C4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_50 0x4E8F1C8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_51 0x4E8F1CC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_52 0x4E8F1D0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_53 0x4E8F1D4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_54 0x4E8F1D8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_55 0x4E8F1DC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_56 0x4E8F1E0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_57 0x4E8F1E4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_58 0x4E8F1E8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_59 0x4E8F1EC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_60 0x4E8F1F0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_61 0x4E8F1F4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_62 0x4E8F1F8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_63 0x4E8F1FC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_0 0x4E8F200



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_1 0x4E8F204



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_2 0x4E8F208



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_3 0x4E8F20C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_4 0x4E8F210



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_5 0x4E8F214



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_6 0x4E8F218



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_7 0x4E8F21C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_8 0x4E8F220



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_9 0x4E8F224



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_10 0x4E8F228



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_11 0x4E8F22C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_12 0x4E8F230



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_13 0x4E8F234



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_14 0x4E8F238



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_15 0x4E8F23C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_16 0x4E8F240



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_17 0x4E8F244



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_18 0x4E8F248



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_19 0x4E8F24C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_20 0x4E8F250



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_21 0x4E8F254



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_22 0x4E8F258



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_23 0x4E8F25C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_24 0x4E8F260



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_25 0x4E8F264



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_26 0x4E8F268



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_27 0x4E8F26C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_28 0x4E8F270



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_29 0x4E8F274



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_30 0x4E8F278



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_31 0x4E8F27C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_32 0x4E8F280



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_33 0x4E8F284



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_34 0x4E8F288



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_35 0x4E8F28C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_36 0x4E8F290



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_37 0x4E8F294



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_38 0x4E8F298



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_39 0x4E8F29C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_40 0x4E8F2A0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_41 0x4E8F2A4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_42 0x4E8F2A8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_43 0x4E8F2AC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_44 0x4E8F2B0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_45 0x4E8F2B4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_46 0x4E8F2B8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_47 0x4E8F2BC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_48 0x4E8F2C0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_49 0x4E8F2C4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_50 0x4E8F2C8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_51 0x4E8F2CC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_52 0x4E8F2D0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_53 0x4E8F2D4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_54 0x4E8F2D8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_55 0x4E8F2DC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_56 0x4E8F2E0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_57 0x4E8F2E4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_58 0x4E8F2E8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_59 0x4E8F2EC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_60 0x4E8F2F0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_61 0x4E8F2F4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_62 0x4E8F2F8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_63 0x4E8F2FC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_0 0x4E8F300



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_1 0x4E8F304



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_2 0x4E8F308



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_3 0x4E8F30C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_4 0x4E8F310



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_5 0x4E8F314



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_6 0x4E8F318



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_7 0x4E8F31C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_8 0x4E8F320



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_9 0x4E8F324



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_10 0x4E8F328



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_11 0x4E8F32C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_12 0x4E8F330



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_13 0x4E8F334



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_14 0x4E8F338



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_15 0x4E8F33C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_16 0x4E8F340



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_17 0x4E8F344



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_18 0x4E8F348



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_19 0x4E8F34C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_20 0x4E8F350



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_21 0x4E8F354



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_22 0x4E8F358



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_23 0x4E8F35C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_24 0x4E8F360



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_25 0x4E8F364



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_26 0x4E8F368



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_27 0x4E8F36C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_28 0x4E8F370



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_29 0x4E8F374



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_30 0x4E8F378



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_31 0x4E8F37C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_32 0x4E8F380



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_33 0x4E8F384



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_34 0x4E8F388



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_35 0x4E8F38C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_36 0x4E8F390



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_37 0x4E8F394



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_38 0x4E8F398



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_39 0x4E8F39C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_40 0x4E8F3A0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_41 0x4E8F3A4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_42 0x4E8F3A8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_43 0x4E8F3AC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_44 0x4E8F3B0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_45 0x4E8F3B4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_46 0x4E8F3B8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_47 0x4E8F3BC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_48 0x4E8F3C0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_49 0x4E8F3C4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_50 0x4E8F3C8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_51 0x4E8F3CC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_52 0x4E8F3D0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_53 0x4E8F3D4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_54 0x4E8F3D8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_55 0x4E8F3DC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_56 0x4E8F3E0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_57 0x4E8F3E4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_58 0x4E8F3E8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_59 0x4E8F3EC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_60 0x4E8F3F0



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_61 0x4E8F3F4



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_62 0x4E8F3F8



#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_63 0x4E8F3FC



#define mmARC_FARM_ARC0_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x4E8F400



#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x4E8F404



#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x4E8F408



#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x4E8F40C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x4E8F410



#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x4E8F414



#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x4E8F418



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x4E8F41C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x4E8F420



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x4E8F424



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x4E8F428



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x4E8F42C



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x4E8F430



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x4E8F434



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x4E8F438



#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG 0x4E8F43C



#endif /* ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ */

drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h

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drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h

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drivers/misc/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0

 *

 * Copyright 2016-2020 HabanaLabs, Ltd.

 * All Rights Reserved.

 *

 */



/************************************

 ** This is an auto-generated file **

 **       DO NOT EDIT BELOW        **

 ************************************/



#ifndef ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_

#define ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_



/*

 *****************************************

 *   ARC_FARM_ARC0_DUP_ENG_AXUSER

 *   (Prototype: AXUSER)

 *****************************************

 */



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_ASID 0x4E89900



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_MMU_BP 0x4E89904



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER 0x4E89908



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_NO_SNOOP 0x4E8990C



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_REDUCTION 0x4E89910



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_ATOMIC 0x4E89914



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_QOS 0x4E89918



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RSVD 0x4E8991C



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_EMEM_CPAGE 0x4E89920



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_CORE 0x4E89924



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_E2E_COORD 0x4E89928



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_LO 0x4E89930



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_HI 0x4E89934



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_LO 0x4E89938



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_HI 0x4E8993C



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_COORD 0x4E89940



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_LOCK 0x4E89944



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_RSVD 0x4E89948



#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD 0x4E8994C



#endif /* ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ */