Commit 01ecd870 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
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drm/amd/display: Set init freq for DCFCLK DS 



[Description]
- Set init frequency for DCFCLK DS
- For now choose 10Mhz after turning off all pipes on init
- DCN32 spreadsheet shows 8Mhz is min for any display config

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2710d6c1

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -696,6 +696,7 @@ static void dcn32_initialize_min_clocks(struct dc *dc) 
{

	struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;



	clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;

	clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

	clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

	clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#define DCN3_2_MBLK_HEIGHT_4BPE 128

#define DCN3_2_MBLK_HEIGHT_8BPE 64

#define DCN3_2_VMIN_DISPCLK_HZ 717000000

#define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq



#define TO_DCN32_RES_POOL(pool)\

	container_of(pool, struct dcn32_resource_pool, base)