Commit 0338f0c2 authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
Browse files

staging: r8192ee: Add the files in the rtl8192ee directory 



These files are specific to the RTL8192EE

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e22f4eda

drivers/staging/rtl8192ee/rtl8192ee/def.h

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/******************************************************************************

 *

 * Copyright(c) 2009-2010  Realtek Corporation.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of version 2 of the GNU General Public License as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program; if not, write to the Free Software Foundation, Inc.,

 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

 *

 * The full GNU General Public License is included in this distribution in the

 * file called LICENSE.

 *

 * Contact Information:

 * wlanfae <wlanfae@realtek.com>

 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,

 * Hsinchu 300, Taiwan.

 *

 * Larry Finger <Larry.Finger@lwfinger.net>

 *

 *****************************************************************************/



#ifndef __RTL92E_DEF_H__

#define __RTL92E_DEF_H__



#define RX_DESC_NUM_92E					512



#define HAL_PRIME_CHNL_OFFSET_DONT_CARE			0

#define HAL_PRIME_CHNL_OFFSET_LOWER			1

#define HAL_PRIME_CHNL_OFFSET_UPPER			2



#define RX_MPDU_QUEUE					0



#define IS_HT_RATE(_rate)	\

	(_rate >= DESC92C_RATEMCS0)

#define IS_CCK_RATE(_rate)	\

	(_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M)

#define IS_OFDM_RATE(_rate)	\

	(_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M)





enum version_8192e {

	VERSION_TEST_CHIP_2T2R_8192E = 0x0024,

	VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C,

	VERSION_UNKNOWN = 0xFF,

};



enum rx_packet_type {

	NORMAL_RX,

	TX_REPORT1,

	TX_REPORT2,

	HIS_REPORT,

	C2H_PACKET,

};



enum rtl_desc_qsel {

	QSLT_BK = 0x2,

	QSLT_BE = 0x0,

	QSLT_VI = 0x5,

	QSLT_VO = 0x7,

	QSLT_BEACON = 0x10,

	QSLT_HIGH = 0x11,

	QSLT_MGNT = 0x12,

	QSLT_CMD = 0x13,

};



enum rtl_desc92c_rate {

	DESC92C_RATE1M = 0x00,

	DESC92C_RATE2M = 0x01,

	DESC92C_RATE5_5M = 0x02,

	DESC92C_RATE11M = 0x03,



	DESC92C_RATE6M = 0x04,

	DESC92C_RATE9M = 0x05,

	DESC92C_RATE12M = 0x06,

	DESC92C_RATE18M = 0x07,

	DESC92C_RATE24M = 0x08,

	DESC92C_RATE36M = 0x09,

	DESC92C_RATE48M = 0x0a,

	DESC92C_RATE54M = 0x0b,



	DESC92C_RATEMCS0 = 0x0c,

	DESC92C_RATEMCS1 = 0x0d,

	DESC92C_RATEMCS2 = 0x0e,

	DESC92C_RATEMCS3 = 0x0f,

	DESC92C_RATEMCS4 = 0x10,

	DESC92C_RATEMCS5 = 0x11,

	DESC92C_RATEMCS6 = 0x12,

	DESC92C_RATEMCS7 = 0x13,

	DESC92C_RATEMCS8 = 0x14,

	DESC92C_RATEMCS9 = 0x15,

	DESC92C_RATEMCS10 = 0x16,

	DESC92C_RATEMCS11 = 0x17,

	DESC92C_RATEMCS12 = 0x18,

	DESC92C_RATEMCS13 = 0x19,

	DESC92C_RATEMCS14 = 0x1a,

	DESC92C_RATEMCS15 = 0x1b,

};

#endif

drivers/staging/rtl8192ee/rtl8192ee/dm.c

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drivers/staging/rtl8192ee/rtl8192ee/dm.h

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/******************************************************************************

 *

 * Copyright(c) 2009-2010  Realtek Corporation.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of version 2 of the GNU General Public License as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program; if not, write to the Free Software Foundation, Inc.,

 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

 *

 * The full GNU General Public License is included in this distribution in the

 * file called LICENSE.

 *

 * Contact Information:

 * wlanfae <wlanfae@realtek.com>

 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,

 * Hsinchu 300, Taiwan.

 *

 * Larry Finger <Larry.Finger@lwfinger.net>

 *

 *****************************************************************************/



#ifndef	__RTL92E_DM_H__

#define __RTL92E_DM_H__



#define	OFDMCCA_TH				500

#define	BW_IND_BIAS				500

#define	MF_USC					2

#define	MF_LSC					1

#define	MF_USC_LSC				0

#define	MONITOR_TIME				30



#define	MAIN_ANT				0

#define	AUX_ANT					1

#define	MAIN_ANT_CG_TRX				1

#define	AUX_ANT_CG_TRX				0

#define	MAIN_ANT_CGCS_RX			0

#define	AUX_ANT_CGCS_RX				1



/*RF REG LIST*/

#define	DM_REG_RF_MODE_11N			0x00

#define	DM_REG_RF_0B_11N			0x0B

#define	DM_REG_CHNBW_11N			0x18

#define	DM_REG_T_METER_11N			0x24

#define	DM_REG_RF_25_11N			0x25

#define	DM_REG_RF_26_11N			0x26

#define	DM_REG_RF_27_11N			0x27

#define	DM_REG_RF_2B_11N			0x2B

#define	DM_REG_RF_2C_11N			0x2C

#define	DM_REG_RXRF_A3_11N			0x3C

#define	DM_REG_T_METER_92D_11N			0x42

#define	DM_REG_T_METER_92E_11N			0x42







/*BB REG LIST*/

/*PAGE 8 */

#define	DM_REG_BB_CTRL_11N			0x800

#define	DM_REG_RF_PIN_11N			0x804

#define	DM_REG_PSD_CTRL_11N			0x808

#define	DM_REG_TX_ANT_CTRL_11N			0x80C

#define	DM_REG_BB_PWR_SAV5_11N			0x818

#define	DM_REG_CCK_RPT_FORMAT_11N		0x824

#define	DM_REG_RX_DEFUALT_A_11N			0x858

#define	DM_REG_RX_DEFUALT_B_11N			0x85A

#define	DM_REG_BB_PWR_SAV3_11N			0x85C

#define	DM_REG_ANTSEL_CTRL_11N			0x860

#define	DM_REG_RX_ANT_CTRL_11N			0x864

#define	DM_REG_PIN_CTRL_11N			0x870

#define	DM_REG_BB_PWR_SAV1_11N			0x874

#define	DM_REG_ANTSEL_PATH_11N			0x878

#define	DM_REG_BB_3WIRE_11N			0x88C

#define	DM_REG_SC_CNT_11N			0x8C4

#define	DM_REG_PSD_DATA_11N			0x8B4

/*PAGE 9*/

#define	DM_REG_ANT_MAPPING1_11N			0x914

#define	DM_REG_ANT_MAPPING2_11N			0x918

/*PAGE A*/

#define	DM_REG_CCK_ANTDIV_PARA1_11N		0xA00

#define	DM_REG_CCK_CCA_11N			0xA0A

#define	DM_REG_CCK_ANTDIV_PARA2_11N		0xA0C

#define	DM_REG_CCK_ANTDIV_PARA3_11N		0xA10

#define	DM_REG_CCK_ANTDIV_PARA4_11N		0xA14

#define	DM_REG_CCK_FILTER_PARA1_11N		0xA22

#define	DM_REG_CCK_FILTER_PARA2_11N		0xA23

#define	DM_REG_CCK_FILTER_PARA3_11N		0xA24

#define	DM_REG_CCK_FILTER_PARA4_11N		0xA25

#define	DM_REG_CCK_FILTER_PARA5_11N		0xA26

#define	DM_REG_CCK_FILTER_PARA6_11N		0xA27

#define	DM_REG_CCK_FILTER_PARA7_11N		0xA28

#define	DM_REG_CCK_FILTER_PARA8_11N		0xA29

#define	DM_REG_CCK_FA_RST_11N			0xA2C

#define	DM_REG_CCK_FA_MSB_11N			0xA58

#define	DM_REG_CCK_FA_LSB_11N			0xA5C

#define	DM_REG_CCK_CCA_CNT_11N			0xA60

#define	DM_REG_BB_PWR_SAV4_11N			0xA74

/*PAGE B */

#define	DM_REG_LNA_SWITCH_11N			0xB2C

#define	DM_REG_PATH_SWITCH_11N			0xB30

#define	DM_REG_RSSI_CTRL_11N			0xB38

#define	DM_REG_CONFIG_ANTA_11N			0xB68

#define	DM_REG_RSSI_BT_11N			0xB9C

/*PAGE C */

#define	DM_REG_OFDM_FA_HOLDC_11N		0xC00

#define	DM_REG_RX_PATH_11N			0xC04

#define	DM_REG_TRMUX_11N			0xC08

#define	DM_REG_OFDM_FA_RSTC_11N			0xC0C

#define	DM_REG_RXIQI_MATRIX_11N			0xC14

#define	DM_REG_TXIQK_MATRIX_LSB1_11N		0xC4C

#define	DM_REG_IGI_A_11N			0xC50

#define	DM_REG_ANTDIV_PARA2_11N			0xC54

#define	DM_REG_IGI_B_11N			0xC58

#define	DM_REG_ANTDIV_PARA3_11N			0xC5C

#define DM_REG_L1SBD_PD_CH_11N			0XC6C

#define	DM_REG_BB_PWR_SAV2_11N			0xC70

#define	DM_REG_RX_OFF_11N			0xC7C

#define	DM_REG_TXIQK_MATRIXA_11N		0xC80

#define	DM_REG_TXIQK_MATRIXB_11N		0xC88

#define	DM_REG_TXIQK_MATRIXA_LSB2_11N		0xC94

#define	DM_REG_TXIQK_MATRIXB_LSB2_11N		0xC9C

#define	DM_REG_RXIQK_MATRIX_LSB_11N		0xCA0

#define	DM_REG_ANTDIV_PARA1_11N			0xCA4

#define	DM_REG_OFDM_FA_TYPE1_11N		0xCF0

/*PAGE D */

#define	DM_REG_OFDM_FA_RSTD_11N			0xD00

#define	DM_REG_OFDM_FA_TYPE2_11N		0xDA0

#define	DM_REG_OFDM_FA_TYPE3_11N		0xDA4

#define	DM_REG_OFDM_FA_TYPE4_11N		0xDA8

/*PAGE E */

#define	DM_REG_TXAGC_A_6_18_11N			0xE00

#define	DM_REG_TXAGC_A_24_54_11N		0xE04

#define	DM_REG_TXAGC_A_1_MCS32_11N		0xE08

#define	DM_REG_TXAGC_A_MCS0_3_11N		0xE10

#define	DM_REG_TXAGC_A_MCS4_7_11N		0xE14

#define	DM_REG_TXAGC_A_MCS8_11_11N		0xE18

#define	DM_REG_TXAGC_A_MCS12_15_11N		0xE1C

#define	DM_REG_FPGA0_IQK_11N			0xE28

#define	DM_REG_TXIQK_TONE_A_11N			0xE30

#define	DM_REG_RXIQK_TONE_A_11N			0xE34

#define	DM_REG_TXIQK_PI_A_11N			0xE38

#define	DM_REG_RXIQK_PI_A_11N			0xE3C

#define	DM_REG_TXIQK_11N			0xE40

#define	DM_REG_RXIQK_11N			0xE44

#define	DM_REG_IQK_AGC_PTS_11N			0xE48

#define	DM_REG_IQK_AGC_RSP_11N			0xE4C

#define	DM_REG_BLUETOOTH_11N			0xE6C

#define	DM_REG_RX_WAIT_CCA_11N			0xE70

#define	DM_REG_TX_CCK_RFON_11N			0xE74

#define	DM_REG_TX_CCK_BBON_11N			0xE78

#define	DM_REG_OFDM_RFON_11N			0xE7C

#define	DM_REG_OFDM_BBON_11N			0xE80

#define		DM_REG_TX2RX_11N		0xE84

#define	DM_REG_TX2TX_11N			0xE88

#define	DM_REG_RX_CCK_11N			0xE8C

#define	DM_REG_RX_OFDM_11N			0xED0

#define	DM_REG_RX_WAIT_RIFS_11N			0xED4

#define	DM_REG_RX2RX_11N			0xED8

#define	DM_REG_STANDBY_11N			0xEDC

#define	DM_REG_SLEEP_11N			0xEE0

#define	DM_REG_PMPD_ANAEN_11N			0xEEC





/*MAC REG LIST*/

#define	DM_REG_BB_RST_11N			0x02

#define	DM_REG_ANTSEL_PIN_11N			0x4C

#define	DM_REG_EARLY_MODE_11N			0x4D0

#define	DM_REG_RSSI_MONITOR_11N			0x4FE

#define	DM_REG_EDCA_VO_11N			0x500

#define	DM_REG_EDCA_VI_11N			0x504

#define	DM_REG_EDCA_BE_11N			0x508

#define	DM_REG_EDCA_BK_11N			0x50C

#define	DM_REG_TXPAUSE_11N			0x522

#define	DM_REG_RESP_TX_11N			0x6D8

#define	DM_REG_ANT_TRAIN_PARA1_11N		0x7b0

#define	DM_REG_ANT_TRAIN_PARA2_11N		0x7b4





/*DIG Related*/

#define	DM_BIT_IGI_11N				0x0000007F







#define HAL_DM_DIG_DISABLE			BIT(0)

#define HAL_DM_HIPWR_DISABLE			BIT(1)



#define OFDM_TABLE_LENGTH			43

#define CCK_TABLE_LENGTH			33



#define OFDM_TABLE_SIZE				43

#define CCK_TABLE_SIZE				33



#define BW_AUTO_SWITCH_HIGH_LOW			25

#define BW_AUTO_SWITCH_LOW_HIGH			30



#define DM_DIG_THRESH_HIGH			40

#define DM_DIG_THRESH_LOW			35



#define DM_FALSEALARM_THRESH_LOW		400

#define DM_FALSEALARM_THRESH_HIGH		1000



#define DM_DIG_MAX				0x3e

#define DM_DIG_MIN				0x1e



#define DM_DIG_MAX_AP				0x32

#define DM_DIG_MIN_AP				0x20



#define DM_DIG_FA_UPPER				0x3e

#define DM_DIG_FA_LOWER				0x1e

#define DM_DIG_FA_TH0				0x200

#define DM_DIG_FA_TH1				0x300

#define DM_DIG_FA_TH2				0x400



#define DM_DIG_BACKOFF_MAX			12

#define DM_DIG_BACKOFF_MIN			-4

#define DM_DIG_BACKOFF_DEFAULT			10



#define RXPATHSELECTION_SS_TH_lOW		30

#define RXPATHSELECTION_DIFF_TH			18



#define DM_RATR_STA_INIT			0

#define DM_RATR_STA_HIGH			1

#define DM_RATR_STA_MIDDLE			2

#define DM_RATR_STA_LOW				3



#define CTS2SELF_THVAL				30

#define REGC38_TH				20



#define WAIOTTHVal				25



#define TXHIGHPWRLEVEL_NORMAL			0

#define TXHIGHPWRLEVEL_LEVEL1			1

#define TXHIGHPWRLEVEL_LEVEL2			2

#define TXHIGHPWRLEVEL_BT1			3

#define TXHIGHPWRLEVEL_BT2			4



#define DM_TYPE_BYFW				0

#define DM_TYPE_BYDRIVER			1



#define TX_POWER_NEAR_FIELD_THRESH_LVL2		74

#define TX_POWER_NEAR_FIELD_THRESH_LVL1		67

#define TXPWRTRACK_MAX_IDX			6



/* Dynamic ATC switch */

#define ATC_STATUS_OFF				0x0	/* enable */

#define	ATC_STATUS_ON				0x1	/* disable */

#define	CFO_THRESHOLD_XTAL			10	/* kHz */

#define	CFO_THRESHOLD_ATC			80	/* kHz */



/* RSSI Dump Message */

#define RA_RSSIDUMP				0xcb0

#define RB_RSSIDUMP				0xcb1

#define RS1_RXEVMDUMP				0xcb2

#define RS2_RXEVMDUMP				0xcb3

#define RA_RXSNRDUMP				0xcb4

#define RB_RXSNRDUMP				0xcb5

#define RA_CFOSHORTDUMP				0xcb6

#define RB_CFOSHORTDUMP				0xcb8

#define RA_CFOLONGDUMP				0xcba

#define RB_CFOLONGDUMP				0xcbc



struct ps_t {

	u8 pre_ccastate;

	u8 cur_ccasate;

	u8 pre_rfstate;

	u8 cur_rfstate;

	long rssi_val_min;



};



struct dig_t {

	u8 dig_enable_flag;

	u8 dig_ext_port_stage;

	u32 rssi_lowthresh;

	u32 rssi_highthresh;



	u32 fa_lowthresh;

	u32 fa_highthresh;



	u8 cursta_connectctate;

	u8 presta_connectstate;

	u8 curmultista_connectstate;



	u8 pre_igvalue;

	u8 cur_igvalue;

	u8 backup_igvalue;

	u8 bt30_cur_igi;

	u8 stop_dig;



	char backoff_val;

	char backoff_val_range_max;

	char backoff_val_range_min;

	u8 rx_gain_range_max;

	u8 rx_gain_range_min;

	u8 rssi_val_min;



	u8 pre_cck_cca_thres;

	u8 cur_cck_cca_thres;

	u8 pre_cck_pd_state;

	u8 cur_cck_pd_state;



	u8 large_fa_hit;

	u8 forbidden_igi;

	u32 recover_cnt;



	char th_l2h_ini;

	char th_edcca_hl_diff;

	char igi_base;

	u8 igi_target;

	bool force_edcca;

	u8 adapen_rssi;



	u8 dig_dynamic_min_0;

	u8 dig_dynamic_min_1;

	bool b_media_connect_0;

	bool b_media_connect_1;



	u32 antdiv_rssi_max;

	u32 rssi_max;

};



enum pwr_track_control_method {

	BBSWING,

	TXAGC

};



extern struct dig_t dm_dig;

void rtl92ee_dm_init(struct ieee80211_hw *hw);

void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);

void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,

				    u8 cur_thres);

void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);

void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);

void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);

void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,

				    u8 rate, bool collision_state);

#endif

drivers/staging/rtl8192ee/rtl8192ee/fw.c

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drivers/staging/rtl8192ee/rtl8192ee/fw.h

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/******************************************************************************

 *

 * Copyright(c) 2009-2010  Realtek Corporation.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of version 2 of the GNU General Public License as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program; if not, write to the Free Software Foundation, Inc.,

 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

 *

 * The full GNU General Public License is included in this distribution in the

 * file called LICENSE.

 *

 * Contact Information:

 * wlanfae <wlanfae@realtek.com>

 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,

 * Hsinchu 300, Taiwan.

 * Larry Finger <Larry.Finger@lwfinger.net>

 *

 *****************************************************************************/



#ifndef __RTL92E__FW__H__

#define __RTL92E__FW__H__



#define FW_8192C_SIZE				0x8000

#define FW_8192C_START_ADDRESS			0x1000

#define FW_8192C_END_ADDRESS			0x5FFF

#define FW_8192C_PAGE_SIZE			4096

#define FW_8192C_POLLING_DELAY			5

#define FW_8192C_POLLING_TIMEOUT_COUNT		3000



#define IS_FW_HEADER_EXIST(_pfwhdr)	\

	((_pfwhdr->signature&0xFFF0) == 0x92E0)

#define USE_OLD_WOWLAN_DEBUG_FW 0



#define H2C_92E_RSVDPAGE_LOC_LEN		5

#define H2C_92E_PWEMODE_LENGTH			5

#define H2C_92E_JOINBSSRPT_LENGTH		1

#define H2C_92E_AP_OFFLOAD_LENGTH		3

#define H2C_92E_WOWLAN_LENGTH			3

#define H2C_92E_KEEP_ALIVE_CTRL_LENGTH		3

#if (USE_OLD_WOWLAN_DEBUG_FW == 0)

#define H2C_92E_REMOTE_WAKE_CTRL_LEN		1

#else

#define H2C_92E_REMOTE_WAKE_CTRL_LEN		3

#endif

#define H2C_92E_AOAC_GLOBAL_INFO_LEN		2

#define H2C_92E_AOAC_RSVDPAGE_LOC_LEN		7





/* Fw PS state for RPWM.

*BIT[2:0] = HW state

*BIT[3] = Protocol PS state,  1: register active state, 0: register sleep state

*BIT[4] = sub-state

*/

#define	FW_PS_RF_ON		BIT(2)

#define	FW_PS_REGISTER_ACTIVE	BIT(3)



#define	FW_PS_ACK		BIT(6)

#define	FW_PS_TOGGLE		BIT(7)



 /* 92E RPWM value*/

 /* BIT[0] = 1: 32k, 0: 40M*/

#define	FW_PS_CLOCK_OFF		BIT(0)		/* 32k */

#define	FW_PS_CLOCK_ON		0		/* 40M */



#define	FW_PS_STATE_MASK		(0x0F)

#define	FW_PS_STATE_HW_MASK		(0x07)

#define	FW_PS_STATE_INT_MASK		(0x3F)



#define	FW_PS_STATE(x)			(FW_PS_STATE_MASK & (x))



#define	FW_PS_STATE_ALL_ON_92E		(FW_PS_CLOCK_ON)

#define	FW_PS_STATE_RF_ON_92E		(FW_PS_CLOCK_ON)

#define	FW_PS_STATE_RF_OFF_92E		(FW_PS_CLOCK_ON)

#define	FW_PS_STATE_RF_OFF_LOW_PWR	(FW_PS_CLOCK_OFF)



/* For 92E H2C PwrMode Cmd ID 5.*/

#define	FW_PWR_STATE_ACTIVE	((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))

#define	FW_PWR_STATE_RF_OFF	0



#define	FW_PS_IS_ACK(x)		((x) & FW_PS_ACK)



#define	IS_IN_LOW_POWER_STATE_92E(FwPSState)		\

	(FW_PS_STATE(FwPSState) == FW_PS_CLOCK_OFF)



#define	FW_PWR_STATE_ACTIVE	((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))

#define	FW_PWR_STATE_RF_OFF	0



struct rtl92c_firmware_header {

	u16 signature;

	u8 category;

	u8 function;

	u16 version;

	u8 subversion;

	u8 rsvd1;

	u8 month;

	u8 date;

	u8 hour;

	u8 minute;

	u16 ramcodeSize;

	u16 rsvd2;

	u32 svnindex;

	u32 rsvd3;

	u32 rsvd4;

	u32 rsvd5;

};



enum rtl8192c_h2c_cmd {

	H2C_92E_RSVDPAGE = 0,

	H2C_92E_MSRRPT = 1,

	H2C_92E_SCAN = 2,

	H2C_92E_KEEP_ALIVE_CTRL = 3,

	H2C_92E_DISCONNECT_DECISION = 4,

#if (USE_OLD_WOWLAN_DEBUG_FW == 1)

	H2C_92E_WO_WLAN = 5,

#endif

	H2C_92E_INIT_OFFLOAD = 6,

#if (USE_OLD_WOWLAN_DEBUG_FW == 1)

	H2C_92E_REMOTE_WAKE_CTRL = 7,

#endif

	H2C_92E_AP_OFFLOAD = 8,

	H2C_92E_BCN_RSVDPAGE = 9,

	H2C_92E_PROBERSP_RSVDPAGE = 10,



	H2C_92E_SETPWRMODE = 0x20,

	H2C_92E_PS_TUNING_PARA = 0x21,

	H2C_92E_PS_TUNING_PARA2 = 0x22,

	H2C_92E_PS_LPS_PARA = 0x23,

	H2C_92E_P2P_PS_OFFLOAD = 024,



#if (USE_OLD_WOWLAN_DEBUG_FW == 0)

	H2C_92E_WO_WLAN = 0x80,

	H2C_92E_REMOTE_WAKE_CTRL = 0x81,

	H2C_92E_AOAC_GLOBAL_INFO = 0x82,

	H2C_92E_AOAC_RSVDPAGE = 0x83,

#endif

	H2C_92E_RA_MASK = 0x40,

	H2C_92E_RSSI_REPORT = 0x42,

	H2C_92E_SELECTIVE_SUSPEND_ROF_CMD,

	H2C_92E_P2P_PS_MODE,

	H2C_92E_PSD_RESULT,

	/*Not defined CTW CMD for P2P yet*/

	H2C_92E_P2P_PS_CTW_CMD,

	MAX_92E_H2CCMD

};



enum rtl8192e_c2h_evt {

	C2H_8192E_DBG = 0,

	C2H_8192E_LB = 1,

	C2H_8192E_TXBF = 2,

	C2H_8192E_TX_REPORT = 3,

	C2H_8192E_BT_INFO = 9,

	C2H_8192E_BT_MP = 11,

	C2H_8192E_RA_RPT = 12,

	MAX_8192E_C2HEVENT

};



#define pagenum_128(_len)	\

	(u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0))



#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val)			\

	SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)

#define SET_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __val)			\

	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __val)

#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __val)		\

	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __val)

#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__pH2CCmd, __val)	\

	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __val)

#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __val)	\

	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __val)

#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __val)		\

	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __val)

#define GET_92E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)			\

	LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)



#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val)		\

	SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)

#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val)		\

	SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)

#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val)		\

	SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)

#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val)		\

	SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)



/* _MEDIA_STATUS_RPT_PARM_CMD1 */

#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)		\

	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)

#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)		\

	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)

#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)		\

	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)

#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)		\

	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)





int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw);

void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,

			  u32 cmd_len, u8 *p_cmdbuffer);

void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw);

void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);

void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus);

void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);

void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);

void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len);

#endif