Loading drivers/spi/Kconfig +1 −1 Original line number Original line Diff line number Diff line Loading @@ -505,7 +505,7 @@ config SPI_TEGRA20_SLINK config SPI_TOPCLIFF_PCH config SPI_TOPCLIFF_PCH tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI" tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI" depends on PCI depends on PCI && (X86_32 || COMPILE_TEST) help help SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus used in some x86 embedded processors. used in some x86 embedded processors. Loading drivers/spi/spi-qup.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -287,7 +287,7 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); if (!xfer) { if (!xfer) { dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n", dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n", qup_err, spi_err, opflags); qup_err, spi_err, opflags); return IRQ_HANDLED; return IRQ_HANDLED; } } Loading Loading @@ -366,7 +366,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) n_words = xfer->len / w_size; n_words = xfer->len / w_size; controller->w_size = w_size; controller->w_size = w_size; if (n_words <= controller->in_fifo_sz) { if (n_words <= (controller->in_fifo_sz / sizeof(u32))) { mode = QUP_IO_M_MODE_FIFO; mode = QUP_IO_M_MODE_FIFO; writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); Loading Loading
drivers/spi/Kconfig +1 −1 Original line number Original line Diff line number Diff line Loading @@ -505,7 +505,7 @@ config SPI_TEGRA20_SLINK config SPI_TOPCLIFF_PCH config SPI_TOPCLIFF_PCH tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI" tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI" depends on PCI depends on PCI && (X86_32 || COMPILE_TEST) help help SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus used in some x86 embedded processors. used in some x86 embedded processors. Loading
drivers/spi/spi-qup.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -287,7 +287,7 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); if (!xfer) { if (!xfer) { dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n", dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n", qup_err, spi_err, opflags); qup_err, spi_err, opflags); return IRQ_HANDLED; return IRQ_HANDLED; } } Loading Loading @@ -366,7 +366,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) n_words = xfer->len / w_size; n_words = xfer->len / w_size; controller->w_size = w_size; controller->w_size = w_size; if (n_words <= controller->in_fifo_sz) { if (n_words <= (controller->in_fifo_sz / sizeof(u32))) { mode = QUP_IO_M_MODE_FIFO; mode = QUP_IO_M_MODE_FIFO; writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); Loading