Commit 04131ae2 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v5.20-tag2' of... 

Merge tag 'renesas-pinctrl-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.20 (take two)

  - Add support for the RZ/V2M and R-Car V4H SoCs,
  - Miscellaneous fixes and improvements.
parents 6011c7e9 36611d28

Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ properties: 
      - renesas,pfc-r8a77995    # R-Car D3

      - renesas,pfc-r8a779a0    # R-Car V3U

      - renesas,pfc-r8a779f0    # R-Car S4-8

      - renesas,pfc-r8a779g0    # R-Car V4H

      - renesas,pfc-sh73a0      # SH-Mobile AG5



  reg:

Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml

0 → 100644
+170 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/V2M combined Pin and GPIO controller



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>

  - Phil Edworthy <phil.edworthy@renesas.com>



description:

  The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.

  Pin multiplexing and GPIO configuration is performed on a per-pin basis.

  Each port features up to 16 pins, each of them configurable for GPIO function

  (port mode) or in alternate function mode.

  Up to 8 different alternate function modes exist for each single pin.



properties:

  compatible:

    const: renesas,r9a09g011-pinctrl # RZ/V2M



  reg:

    maxItems: 1



  gpio-controller: true



  '#gpio-cells':

    const: 2

    description:

      The first cell contains the global GPIO port index, constructed using the

      RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the

      second cell represents consumer flag as mentioned in ../gpio/gpio.txt

      E.g. "RZV2M_GPIO(8, 1)" for P8_1.



  gpio-ranges:

    maxItems: 1



  interrupts:

    description: INEXINT[0..38] corresponding to individual pin inputs.

    maxItems: 39



  clocks:

    maxItems: 1



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



additionalProperties:

  anyOf:

    - type: object

      allOf:

        - $ref: pincfg-node.yaml#

        - $ref: pinmux-node.yaml#



      description:

        Pin controller client devices use pin configuration subnodes (children

        and grandchildren) for desired pin configuration.

        Client device subnodes use below standard properties.



      properties:

        phandle: true

        pinmux:

          description:

            Values are constructed from GPIO port number, pin number, and

            alternate function configuration number using the RZV2M_PORT_PINMUX()

            helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.

        pins: true

        bias-disable: true

        bias-pull-down: true

        bias-pull-up: true

        drive-strength-microamp:

          # Superset of supported values

          enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,

                  9000, 9600, 11000, 12000, 13000, 18000 ]

        slew-rate:

          description: 0 is slow slew rate, 1 is fast slew rate

          enum: [ 0, 1 ]

        gpio-hog: true

        gpios: true

        output-high: true

        output-low: true

        line-name: true



    - type: object

      properties:

        phandle: true



      additionalProperties:

        $ref: "#/additionalProperties/anyOf/0"



allOf:

  - $ref: "pinctrl.yaml#"



required:

  - compatible

  - reg

  - gpio-controller

  - '#gpio-cells'

  - gpio-ranges

  - interrupts

  - clocks

  - power-domains

  - resets



examples:

  - |

    #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>

    #include <dt-bindings/clock/r9a09g011-cpg.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    pinctrl: pinctrl@b6250000 {

            compatible = "renesas,r9a09g011-pinctrl";

            reg = <0xb6250000 0x800>;



            gpio-controller;

            #gpio-cells = <2>;

            gpio-ranges = <&pinctrl 0 0 352>;

            interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

            clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;

            resets = <&cpg R9A09G011_PFC_PRESETN>;

            power-domains = <&cpg>;



            i2c2_pins: i2c2 {

                    pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */

                             <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */

            };

    };

drivers/pinctrl/renesas/Kconfig

+18 −0
Original line number Diff line number Diff line
@@ -38,7 +38,9 @@ config PINCTRL_RENESAS 
	select PINCTRL_PFC_R8A77995 if ARCH_R8A77995

	select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0

	select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0

	select PINCTRL_PFC_R8A779G0 if ARCH_R8A779G0

	select PINCTRL_RZG2L if ARCH_RZG2L

	select PINCTRL_RZV2M if ARCH_R9A09G011

	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203

	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -153,6 +155,10 @@ config PINCTRL_PFC_R8A779A0 
	bool "pin control support for R-Car V3U" if COMPILE_TEST

	select PINCTRL_SH_PFC



config PINCTRL_PFC_R8A779G0

	bool "pin control support for R-Car V4H" if COMPILE_TEST

	select PINCTRL_SH_PFC



config PINCTRL_PFC_R8A7740

	bool "pin control support for R-Mobile A1" if COMPILE_TEST

	select PINCTRL_SH_PFC_GPIO
@@ -237,6 +243,18 @@ config PINCTRL_RZN1 
	help

	  This selects pinctrl driver for Renesas RZ/N1 devices.



config PINCTRL_RZV2M

	bool "pin control support for RZ/V2M"

	depends on OF

	depends on ARCH_R9A09G011 || COMPILE_TEST

	select GPIOLIB

	select GENERIC_PINCTRL_GROUPS

	select GENERIC_PINMUX_FUNCTIONS

	select GENERIC_PINCONF

	help

	  This selects GPIO and pinctrl driver for Renesas RZ/V2M

	  platforms.



config PINCTRL_PFC_SH7203

	bool "pin control support for SH7203" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO

drivers/pinctrl/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o 
obj-$(CONFIG_PINCTRL_PFC_R8A77995)	+= pfc-r8a77995.o

obj-$(CONFIG_PINCTRL_PFC_R8A779A0)	+= pfc-r8a779a0.o

obj-$(CONFIG_PINCTRL_PFC_R8A779F0)	+= pfc-r8a779f0.o

obj-$(CONFIG_PINCTRL_PFC_R8A779G0)	+= pfc-r8a779g0.o

obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o

obj-$(CONFIG_PINCTRL_PFC_SH7264)	+= pfc-sh7264.o

obj-$(CONFIG_PINCTRL_PFC_SH7269)	+= pfc-sh7269.o
@@ -49,6 +50,7 @@ obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o 
obj-$(CONFIG_PINCTRL_RZA2)	+= pinctrl-rza2.o

obj-$(CONFIG_PINCTRL_RZG2L)	+= pinctrl-rzg2l.o

obj-$(CONFIG_PINCTRL_RZN1)	+= pinctrl-rzn1.o

obj-$(CONFIG_PINCTRL_RZV2M)	+= pinctrl-rzv2m.o



ifeq ($(CONFIG_COMPILE_TEST),y)

CFLAGS_pfc-sh7203.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a

drivers/pinctrl/renesas/core.c

+6 −0
Original line number Diff line number Diff line
@@ -644,6 +644,12 @@ static const struct of_device_id sh_pfc_of_table[] = { 
		.data = &r8a779f0_pinmux_info,

	},

#endif

#ifdef CONFIG_PINCTRL_PFC_R8A779G0

	{

		.compatible = "renesas,pfc-r8a779g0",

		.data = &r8a779g0_pinmux_info,

	},

#endif

#ifdef CONFIG_PINCTRL_PFC_SH73A0

	{

		.compatible = "renesas,pfc-sh73a0",