Commit 04df0dc1 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools arch x86: Sync the msr-index.h copy with the kernel sources



To pick up the changes from these csets:

  1348924b ("x86/msr: Define new bits in TSX_FORCE_ABORT MSR")

That cause no changes to tooling:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
  $ diff -u before after
  $

Just silences this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'
  diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Cc: Borislav Petkov <bp@suse.de>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 8941ba50
Loading
Loading
Loading
Loading
+4 −0
Original line number Diff line number Diff line
@@ -772,6 +772,10 @@

#define MSR_TFA_RTM_FORCE_ABORT_BIT	0
#define MSR_TFA_RTM_FORCE_ABORT		BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
#define MSR_TFA_TSX_CPUID_CLEAR_BIT	1
#define MSR_TFA_TSX_CPUID_CLEAR		BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
#define MSR_TFA_SDV_ENABLE_RTM_BIT	2
#define MSR_TFA_SDV_ENABLE_RTM		BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)

/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX		0x00000180