Commit 051504d9 authored by Oded Gabbay's avatar Oded Gabbay
Browse files

habanalabs: update firmware files 



Update various firmware header files with new defines.

Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent 293744d9

drivers/misc/habanalabs/include/common/hl_boot_if.h

+17 −0
Original line number Diff line number Diff line
@@ -56,6 +56,20 @@ 
 * CPU_BOOT_ERR0_EFUSE_FAIL		Reading from eFuse failed.

 *					The PCI device ID might be wrong.

 *

 * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL	Verification of primary image failed.

 *					It mean that ppboot checksum

 *					verification for the preboot primary

 *					image has failed to match expected

 *					checksum. Trying to program image again

 *					might solve this.

 *

 * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL	Verification of secondary image failed.

 *					It mean that ppboot checksum

 *					verification for the preboot secondary

 *					image has failed to match expected

 *					checksum. Trying to program image again

 *					might solve this.

 *

 * CPU_BOOT_ERR0_ENABLED		Error registers enabled.

 *					This is a main indication that the

 *					running FW populates the error
@@ -72,6 +86,8 @@ 
#define CPU_BOOT_ERR0_SECURITY_NOT_RDY		(1 << 7)

#define CPU_BOOT_ERR0_SECURITY_FAIL		(1 << 8)

#define CPU_BOOT_ERR0_EFUSE_FAIL		(1 << 9)

#define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL		(1 << 10)

#define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL		(1 << 11)

#define CPU_BOOT_ERR0_ENABLED			(1 << 31)



/*
@@ -141,6 +157,7 @@ 
 *					bits are not garbage, but actual

 *					statuses.

 *					Initialized in: preboot

 *

 */

#define CPU_BOOT_DEV_STS0_SECURITY_EN			(1 << 0)

#define CPU_BOOT_DEV_STS0_DEBUG_EN			(1 << 1)

drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h

+2 −1
Original line number Diff line number Diff line
@@ -30,7 +30,8 @@ enum gaudi_pll_index { 
	MESH_PLL,

	MME_PLL,

	TPC_PLL,

	IF_PLL

	IF_PLL,

	PLL_MAX

};



enum gaudi_nic_axi_error {

drivers/misc/habanalabs/include/goya/goya_fw_if.h

+2 −1
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ enum goya_pll_index { 
	MME_PLL,

	PCI_PLL,

	EMMC_PLL,

	TPC_PLL

	TPC_PLL,

	PLL_MAX

};



#define GOYA_PLL_FREQ_LOW		50000000 /* 50 MHz */