Commit 0544f32b authored by James Clark's avatar James Clark Committed by Mathieu Poirier
Browse files

coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses 



This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.

Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-13-james.clark@arm.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent f5def772

drivers/hwtracing/coresight/coresight-etm4x-core.c

+1 −1
Original line number Diff line number Diff line
@@ -443,7 +443,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 
	for (i = 0; i < drvdata->nr_ss_cmp; i++) {

		/* always clear status bit on restart if using single-shot */

		if (config->ss_ctrl[i] || config->ss_pe_cmp[i])

			config->ss_status[i] &= ~BIT(31);

			config->ss_status[i] &= ~TRCSSCSRn_STATUS;

		etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));

		etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));

		if (etm4x_sspcicrn_present(drvdata, i))

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c

+3 −3
Original line number Diff line number Diff line
@@ -1792,9 +1792,9 @@ static ssize_t sshot_ctrl_store(struct device *dev, 


	spin_lock(&drvdata->spinlock);

	idx = config->ss_idx;

	config->ss_ctrl[idx] = val & GENMASK(24, 0);

	config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);

	/* must clear bit 31 in related status register on programming */

	config->ss_status[idx] &= ~BIT(31);

	config->ss_status[idx] &= ~TRCSSCSRn_STATUS;

	spin_unlock(&drvdata->spinlock);

	return size;

}
@@ -1844,7 +1844,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, 
	idx = config->ss_idx;

	config->ss_pe_cmp[idx] = val & GENMASK(7, 0);

	/* must clear bit 31 in related status register on programming */

	config->ss_status[idx] &= ~BIT(31);

	config->ss_status[idx] &= ~TRCSSCSRn_STATUS;

	spin_unlock(&drvdata->spinlock);

	return size;

}

drivers/hwtracing/coresight/coresight-etm4x.h

+4 −0
Original line number Diff line number Diff line
@@ -214,6 +214,10 @@ 
#define TRCACATRn_CONTEXTTYPE_VMID		BIT(3)

#define TRCACATRn_CONTEXT_MASK			GENMASK(6, 4)

#define TRCACATRn_EXLEVEL_MASK			GENMASK(14, 8)



#define TRCSSCSRn_STATUS			BIT(31)

#define TRCSSCCRn_SAC_ARC_RST_MASK		GENMASK(24, 0)



/*

 * System instructions to access ETM registers.

 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions