Commit 05674cc9 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Move mclk calculation function to DML 



The function responsible for calculating the MCLK switching has FPU
operations. This commit moves it to the dcn30_fpu file.

Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6a7379f1

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+0 −38
Original line number Diff line number Diff line
@@ -2031,44 +2031,6 @@ void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct 
	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;

}



/*

 * Finds dummy_latency_index when MCLK switching using firmware based

 * vblank stretch is enabled. This function will iterate through the

 * table of dummy pstate latencies until the lowest value that allows

 * dm_allow_self_refresh_and_mclk_switch to happen is found

 */

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,

		display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel)

{

	const int max_latency_table_entries = 4;

	int dummy_latency_index = 0;



	while (dummy_latency_index < max_latency_table_entries) {

		context->bw_ctx.dml.soc.dram_clock_change_latency_us =

				dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

		dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);



		if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==

			dm_allow_self_refresh_and_mclk_switch)

			break;



		dummy_latency_index++;

	}



	if (dummy_latency_index == max_latency_table_entries) {

		ASSERT(dummy_latency_index != max_latency_table_entries);

		/* If the execution gets here, it means dummy p_states are

		 * not possible. This should never happen and would mean

		 * something is severely wrong.

		 * Here we reset dummy_latency_index to 3, because it is

		 * better to have underflows than system crashes.

		 */

		dummy_latency_index = 3;

	}



	return dummy_latency_index;

}



void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

{

	DC_FP_START();

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

+43 −0
Original line number Diff line number Diff line
@@ -616,6 +616,49 @@ void dcn30_fpu_update_bw_bounding_box(struct dc *dc, 


}



/**

 * Finds dummy_latency_index when MCLK switching using firmware based

 * vblank stretch is enabled. This function will iterate through the

 * table of dummy pstate latencies until the lowest value that allows

 * dm_allow_self_refresh_and_mclk_switch to happen is found

 */

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

							    struct dc_state *context,

							    display_e2e_pipe_params_st *pipes,

							    int pipe_cnt,

							    int vlevel)

{

	const int max_latency_table_entries = 4;

	int dummy_latency_index = 0;



	dc_assert_fp_enabled();



	while (dummy_latency_index < max_latency_table_entries) {

		context->bw_ctx.dml.soc.dram_clock_change_latency_us =

				dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

		dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);



		if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==

			dm_allow_self_refresh_and_mclk_switch)

			break;



		dummy_latency_index++;

	}



	if (dummy_latency_index == max_latency_table_entries) {

		ASSERT(dummy_latency_index != max_latency_table_entries);

		/* If the execution gets here, it means dummy p_states are

		 * not possible. This should never happen and would mean

		 * something is severely wrong.

		 * Here we reset dummy_latency_index to 3, because it is

		 * better to have underflows than system crashes.

		 */

		dummy_latency_index = 3;

	}



	return dummy_latency_index;

}



void dcn3_fpu_build_wm_range_table(struct clk_mgr *base)

{

	/* defaults */

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

+6 −0
Original line number Diff line number Diff line
@@ -63,6 +63,12 @@ void dcn30_fpu_update_bw_bounding_box(struct dc *dc, 
	unsigned int *dcfclk_mhz,

	unsigned int *dram_speed_mts);



int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

							    struct dc_state *context,

							    display_e2e_pipe_params_st *pipes,

							    int pipe_cnt,

							    int vlevel);



void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);



#endif /* __DCN30_FPU_H__*/