Loading drivers/gpu/drm/i915/intel_dp.c +34 −22 Original line number Diff line number Diff line Loading @@ -992,10 +992,12 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp) pp &= ~PANEL_UNLOCK_MASK; pp |= PANEL_UNLOCK_REGS; if (IS_GEN5(dev)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); } pp |= POWER_TARGET_ON; I915_WRITE(PCH_PP_CONTROL, pp); Loading @@ -1006,10 +1008,12 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp) DRM_ERROR("panel on wait timed out: 0x%08x\n", I915_READ(PCH_PP_STATUS)); if (IS_GEN5(dev)) { pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); } } static void ironlake_edp_panel_off(struct drm_encoder *encoder) { Loading @@ -1025,11 +1029,19 @@ static void ironlake_edp_panel_off(struct drm_encoder *encoder) pp &= ~PANEL_UNLOCK_MASK; pp |= PANEL_UNLOCK_REGS; if (IS_GEN5(dev)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); } intel_dp->panel_off_jiffies = jiffies; if (IS_GEN5(dev)) { pp &= ~POWER_TARGET_ON; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); pp &= ~POWER_TARGET_ON; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); Loading @@ -1042,7 +1054,7 @@ static void ironlake_edp_panel_off(struct drm_encoder *encoder) pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); intel_dp->panel_off_jiffies = jiffies; } } static void ironlake_edp_backlight_on (struct intel_dp *intel_dp) Loading Loading
drivers/gpu/drm/i915/intel_dp.c +34 −22 Original line number Diff line number Diff line Loading @@ -992,10 +992,12 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp) pp &= ~PANEL_UNLOCK_MASK; pp |= PANEL_UNLOCK_REGS; if (IS_GEN5(dev)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); } pp |= POWER_TARGET_ON; I915_WRITE(PCH_PP_CONTROL, pp); Loading @@ -1006,10 +1008,12 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp) DRM_ERROR("panel on wait timed out: 0x%08x\n", I915_READ(PCH_PP_STATUS)); if (IS_GEN5(dev)) { pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); } } static void ironlake_edp_panel_off(struct drm_encoder *encoder) { Loading @@ -1025,11 +1029,19 @@ static void ironlake_edp_panel_off(struct drm_encoder *encoder) pp &= ~PANEL_UNLOCK_MASK; pp |= PANEL_UNLOCK_REGS; if (IS_GEN5(dev)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); } intel_dp->panel_off_jiffies = jiffies; if (IS_GEN5(dev)) { pp &= ~POWER_TARGET_ON; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); pp &= ~POWER_TARGET_ON; I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); Loading @@ -1042,7 +1054,7 @@ static void ironlake_edp_panel_off(struct drm_encoder *encoder) pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); intel_dp->panel_off_jiffies = jiffies; } } static void ironlake_edp_backlight_on (struct intel_dp *intel_dp) Loading