Commit 05ebc1cc authored by Tudor Ambarus's avatar Tudor Ambarus
Browse files

mtd: spi-nor: spansion: Replace hardcoded values for addr_nbytes/addr_mode_nbytes 



We track in the core the internal address mode of the flash. Stop using
hardcoded values for the number of bytes of address and use
nor->addr_nbytes and nor->params->addr_mode_nbytes instead.

Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: default avatarTakahiro Kuwano <Takahiro.Kuwano@infineon.com>
Link: https://lore.kernel.org/r/20220728041451.85559-2-tudor.ambarus@microchip.com
parent aff1fa41

drivers/mtd/spi-nor/spansion.c

+11 −5
Original line number Diff line number Diff line
@@ -49,11 +49,13 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) 
	struct spi_mem_op op;

	u8 *buf = nor->bouncebuf;

	int ret;

	u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;



	/* Use 24 dummy cycles for memory array reads. */

	*buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;

	op = (struct spi_mem_op)

		CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf);

		CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,

					  SPINOR_REG_CYPRESS_CFR2V, 1, buf);



	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);

	if (ret)
@@ -64,14 +66,16 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) 
	/* Set the octal and DTR enable bits. */

	buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;

	op = (struct spi_mem_op)

		CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf);

		CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,

					  SPINOR_REG_CYPRESS_CFR5V, 1, buf);



	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);

	if (ret)

		return ret;



	/* Read flash ID to make sure the switch was successful. */

	ret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR);

	ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf,

			      SNOR_PROTO_8_8_8_DTR);

	if (ret) {

		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);

		return ret;
@@ -97,7 +101,8 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) 
	buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;

	buf[1] = 0;

	op = (struct spi_mem_op)

		CYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf);

		CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes,

					  SPINOR_REG_CYPRESS_CFR5V, 2, buf);

	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);

	if (ret)

		return ret;
@@ -191,7 +196,8 @@ static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) 
static int cypress_nor_set_page_size(struct spi_nor *nor)

{

	struct spi_mem_op op =

		CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR3V,

		CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,

					  SPINOR_REG_CYPRESS_CFR3V,

					  nor->bouncebuf);

	int ret;