Commit 064f14e9 authored by Serge Semin's avatar Serge Semin Committed by Damien Le Moal
Browse files

dt-bindings: ata: ahci: Add Baikal-T1 AHCI SATA controller DT schema 



Baikal-T1 AHCI controller is based on the DWC AHCI SATA IP-core v4.10a
with the next specific settings: two SATA ports, cascaded CSR access based
on two clock domains (APB and AXI), selectable source of the reference
clock (though stable work is currently available from the external source
only), two reset lanes for the application and SATA ports domains. Other
than that the device is fully compatible with the generic DWC AHCI SATA
bindings.

Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: default avatarHannes Reinecke <hare@suse.de>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDamien Le Moal <damien.lemoal@opensource.wdc.com>
parent 33629d35

Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml

0 → 100644
+115 −0
Original line number Original line Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Baikal-T1 SoC AHCI SATA controller



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description:

  AHCI SATA controller embedded into the Baikal-T1 SoC is based on the

  DWC AHCI SATA v4.10a IP-core.



allOf:

  - $ref: snps,dwc-ahci-common.yaml#



properties:

  compatible:

    const: baikal,bt1-ahci



  clocks:

    items:

      - description: Peripheral APB bus clock

      - description: Application AXI BIU clock

      - description: SATA Ports reference clock



  clock-names:

    items:

      - const: pclk

      - const: aclk

      - const: ref



  resets:

    items:

      - description: Application AXI BIU domain reset

      - description: SATA Ports clock domain reset



  reset-names:

    items:

      - const: arst

      - const: ref



  ports-implemented:

    maximum: 0x3



patternProperties:

  "^sata-port@[0-1]$":

    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port



    properties:

      reg:

        minimum: 0

        maximum: 1



      snps,tx-ts-max:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Due to having AXI3 bus interface utilized the maximum Tx DMA

          transaction size can't exceed 16 beats (AxLEN[3:0]).

        enum: [ 1, 2, 4, 8, 16 ]



      snps,rx-ts-max:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Due to having AXI3 bus interface utilized the maximum Rx DMA

          transaction size can't exceed 16 beats (AxLEN[3:0]).

        enum: [ 1, 2, 4, 8, 16 ]



    unevaluatedProperties: false



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - resets



unevaluatedProperties: false



examples:

  - |

    sata@1f050000 {

      compatible = "baikal,bt1-ahci";

      reg = <0x1f050000 0x2000>;

      #address-cells = <1>;

      #size-cells = <0>;



      interrupts = <0 64 4>;



      clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&sata_ref_clk>;

      clock-names = "pclk", "aclk", "ref";



      resets = <&ccu_axi 2>, <&ccu_sys 0>;

      reset-names = "arst", "ref";



      ports-implemented = <0x3>;



      sata-port@0 {

        reg = <0>;



        snps,tx-ts-max = <4>;

        snps,rx-ts-max = <4>;

      };



      sata-port@1 {

        reg = <1>;



        snps,tx-ts-max = <4>;

        snps,rx-ts-max = <4>;

      };

    };

...