Commit 06bfc045 authored Feb 27, 2021 by Eric Huang Committed by Alex Deucher Mar 23, 2021

drm/amdgpu: set CPU mapping of vram as cached for A+A mode



New A+A HW supports cached vram mapped to cpu.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 761d86d3

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -673,6 +673,9 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso

		mem->bus.offset += adev->gmc.aper_base;
		mem->bus.is_iomem = true;
		if (adev->gmc.xgmi.connected_to_cpu)
		mem->bus.caching = ttm_cached;
		else
		mem->bus.caching = ttm_write_combined;
		break;
		default: