Loading arch/cris/arch-v10/drivers/eeprom.c +3 −3 Original line number Diff line number Diff line /*!***************************************************************************** *! *! Implements an interface for i2c compatible eeproms to run under linux. *! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustents by *! Implements an interface for i2c compatible eeproms to run under Linux. *! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by *! Johan.Adolfsson@axis.com *! *! Probing results: Loading Loading @@ -51,7 +51,7 @@ *! Revision 1.8 2001/06/15 13:24:29 jonashg *! * Added verification of pointers from userspace in read and write. *! * Made busy counter volatile. *! * Added define for inital write delay. *! * Added define for initial write delay. *! * Removed warnings by using loff_t instead of unsigned long. *! *! Revision 1.7 2001/06/14 15:26:54 jonashg Loading arch/cris/arch-v10/drivers/i2c.c +1 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ *! Update Port B register and shadow even when running with hardware support *! to avoid glitches when reading bits *! Never set direction to out in i2c_inbyte *! Removed incorrect clock togling at end of i2c_inbyte *! Removed incorrect clock toggling at end of i2c_inbyte *! *! Revision 1.8 2002/08/13 06:31:53 starvik *! Made SDA and SCL line configurable Loading arch/cris/arch-v10/kernel/kgdb.c +1 −1 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ *! *! Revision 1.2 2002/11/19 14:35:24 starvik *! Changes from linux 2.4 *! Changed struct initializer syntax to the currently prefered notation *! Changed struct initializer syntax to the currently preferred notation *! *! Revision 1.1 2001/12/17 13:59:27 bjornw *! Initial revision Loading arch/ia64/hp/common/sba_iommu.c +4 −4 Original line number Diff line number Diff line Loading @@ -75,7 +75,7 @@ ** If a device prefetches beyond the end of a valid pdir entry, it will cause ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should ** disconnect on 4k boundaries and prevent such issues. If the device is ** particularly agressive, this option will keep the entire pdir valid such ** particularly aggressive, this option will keep the entire pdir valid such ** that prefetching will hit a valid address. This could severely impact ** error containment, and is therefore off by default. The page that is ** used for spill-over is poisoned, so that should help debugging somewhat. Loading Loading @@ -258,10 +258,10 @@ static u64 prefetch_spill_page; /* ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up ** (or rather not merge) DMA's into managable chunks. ** (or rather not merge) DMAs into manageable chunks. ** On parisc, this is more of the software/tuning constraint ** rather than the HW. I/O MMU allocation alogorithms can be ** faster with smaller size is (to some degree). ** rather than the HW. I/O MMU allocation algorithms can be ** faster with smaller sizes (to some degree). */ #define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size) Loading arch/sh64/lib/dbg.c +1 −1 Original line number Diff line number Diff line Loading @@ -383,7 +383,7 @@ void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs) /* ======================================================================= */ /* ** Depending on <base> scan the MMU, Data or Instrction side ** Depending on <base> scan the MMU, Data or Instruction side ** looking for a valid mapping matching Eaddr & asid. ** Return -1 if not found or the TLB id entry otherwise. ** Note: it works only for 4k pages! Loading Loading
arch/cris/arch-v10/drivers/eeprom.c +3 −3 Original line number Diff line number Diff line /*!***************************************************************************** *! *! Implements an interface for i2c compatible eeproms to run under linux. *! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustents by *! Implements an interface for i2c compatible eeproms to run under Linux. *! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by *! Johan.Adolfsson@axis.com *! *! Probing results: Loading Loading @@ -51,7 +51,7 @@ *! Revision 1.8 2001/06/15 13:24:29 jonashg *! * Added verification of pointers from userspace in read and write. *! * Made busy counter volatile. *! * Added define for inital write delay. *! * Added define for initial write delay. *! * Removed warnings by using loff_t instead of unsigned long. *! *! Revision 1.7 2001/06/14 15:26:54 jonashg Loading
arch/cris/arch-v10/drivers/i2c.c +1 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ *! Update Port B register and shadow even when running with hardware support *! to avoid glitches when reading bits *! Never set direction to out in i2c_inbyte *! Removed incorrect clock togling at end of i2c_inbyte *! Removed incorrect clock toggling at end of i2c_inbyte *! *! Revision 1.8 2002/08/13 06:31:53 starvik *! Made SDA and SCL line configurable Loading
arch/cris/arch-v10/kernel/kgdb.c +1 −1 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ *! *! Revision 1.2 2002/11/19 14:35:24 starvik *! Changes from linux 2.4 *! Changed struct initializer syntax to the currently prefered notation *! Changed struct initializer syntax to the currently preferred notation *! *! Revision 1.1 2001/12/17 13:59:27 bjornw *! Initial revision Loading
arch/ia64/hp/common/sba_iommu.c +4 −4 Original line number Diff line number Diff line Loading @@ -75,7 +75,7 @@ ** If a device prefetches beyond the end of a valid pdir entry, it will cause ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should ** disconnect on 4k boundaries and prevent such issues. If the device is ** particularly agressive, this option will keep the entire pdir valid such ** particularly aggressive, this option will keep the entire pdir valid such ** that prefetching will hit a valid address. This could severely impact ** error containment, and is therefore off by default. The page that is ** used for spill-over is poisoned, so that should help debugging somewhat. Loading Loading @@ -258,10 +258,10 @@ static u64 prefetch_spill_page; /* ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up ** (or rather not merge) DMA's into managable chunks. ** (or rather not merge) DMAs into manageable chunks. ** On parisc, this is more of the software/tuning constraint ** rather than the HW. I/O MMU allocation alogorithms can be ** faster with smaller size is (to some degree). ** rather than the HW. I/O MMU allocation algorithms can be ** faster with smaller sizes (to some degree). */ #define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size) Loading
arch/sh64/lib/dbg.c +1 −1 Original line number Diff line number Diff line Loading @@ -383,7 +383,7 @@ void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs) /* ======================================================================= */ /* ** Depending on <base> scan the MMU, Data or Instrction side ** Depending on <base> scan the MMU, Data or Instruction side ** looking for a valid mapping matching Eaddr & asid. ** Return -1 if not found or the TLB id entry otherwise. ** Note: it works only for 4k pages! Loading