Commit 077e5f4f authored by Samuel Holland's avatar Samuel Holland Committed by Jernej Skrabec
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riscv: dts: allwinner: Add the D1/D1s SoC devicetree 



D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
on a single die, or at a pair of dies derived from the same design.

D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
variants.

Because the original design supported both ARM and RISC-V CPUs, some
peripherals are duplicated. In addition, all variants except D1s contain
a HiFi 4 DSP with its own set of peripherals.

The devicetrees are organized to minimize duplication:
 - Common perhiperals are described in sunxi-d1s-t113.dtsi
 - DSP-related peripherals are described in sunxi-d1-t113.dtsi
 - RISC-V specific hardware is described in sun20i-d1s.dtsi
 - Functionality unique to the D1 variant is described in sun20i-d1.dtsi

The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.

Acked-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230126045738.47903-5-samuel@sholland.org


Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
parent a0097fec

arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)

// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>



#include "sun20i-d1s.dtsi"

#include "sunxi-d1-t113.dtsi"



/ {

	soc {

		lradc: keys@2009800 {

			compatible = "allwinner,sun20i-d1-lradc",

				     "allwinner,sun50i-r329-lradc";

			reg = <0x2009800 0x400>;

			interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_LRADC>;

			resets = <&ccu RST_BUS_LRADC>;

			status = "disabled";

		};



		i2s0: i2s@2032000 {

			compatible = "allwinner,sun20i-d1-i2s",

				     "allwinner,sun50i-r329-i2s";

			reg = <0x2032000 0x1000>;

			interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_I2S0>,

				 <&ccu CLK_I2S0>;

			clock-names = "apb", "mod";

			resets = <&ccu RST_BUS_I2S0>;

			dmas = <&dma 3>, <&dma 3>;

			dma-names = "rx", "tx";

			status = "disabled";

			#sound-dai-cells = <0>;

		};

	};

};



&pio {

	/omit-if-no-ref/

	dmic_pb11_d0_pin: dmic-pb11-d0-pin {

		pins = "PB11";

		function = "dmic";

	};



	/omit-if-no-ref/

	dmic_pe17_clk_pin: dmic-pe17-clk-pin {

		pins = "PE17";

		function = "dmic";

	};



	/omit-if-no-ref/

	i2c0_pb10_pins: i2c0-pb10-pins {

		pins = "PB10", "PB11";

		function = "i2c0";

	};



	/omit-if-no-ref/

	i2c2_pb0_pins: i2c2-pb0-pins {

		pins = "PB0", "PB1";

		function = "i2c2";

	};



	/omit-if-no-ref/

	uart0_pb8_pins: uart0-pb8-pins {

		pins = "PB8", "PB9";

		function = "uart0";

	};

};

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)

// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>



#define SOC_PERIPHERAL_IRQ(nr)	(nr + 16)



#include "sunxi-d1s-t113.dtsi"



/ {

	cpus {

		timebase-frequency = <24000000>;

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			compatible = "thead,c906", "riscv";

			device_type = "cpu";

			reg = <0>;

			clocks = <&ccu CLK_RISCV>;

			d-cache-block-size = <64>;

			d-cache-sets = <256>;

			d-cache-size = <32768>;

			i-cache-block-size = <64>;

			i-cache-sets = <128>;

			i-cache-size = <32768>;

			mmu-type = "riscv,sv39";

			operating-points-v2 = <&opp_table_cpu>;

			riscv,isa = "rv64imafdc";

			#cooling-cells = <2>;



			cpu0_intc: interrupt-controller {

				compatible = "riscv,cpu-intc";

				interrupt-controller;

				#address-cells = <0>;

				#interrupt-cells = <1>;

			};

		};

	};



	opp_table_cpu: opp-table-cpu {

		compatible = "operating-points-v2";



		opp-408000000 {

			opp-hz = /bits/ 64 <408000000>;

			opp-microvolt = <900000 900000 1100000>;

		};



		opp-1080000000 {

			opp-hz = /bits/ 64 <1008000000>;

			opp-microvolt = <900000 900000 1100000>;

		};

	};



	soc {

		interrupt-parent = <&plic>;



		riscv_wdt: watchdog@6011000 {

			compatible = "allwinner,sun20i-d1-wdt";

			reg = <0x6011000 0x20>;

			interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dcxo>, <&rtc CLK_OSC32K>;

			clock-names = "hosc", "losc";

		};



		plic: interrupt-controller@10000000 {

			compatible = "allwinner,sun20i-d1-plic",

				     "thead,c900-plic";

			reg = <0x10000000 0x4000000>;

			interrupts-extended = <&cpu0_intc 11>,

					      <&cpu0_intc 9>;

			interrupt-controller;

			riscv,ndev = <175>;

			#address-cells = <0>;

			#interrupt-cells = <2>;

		};

	};

};

arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)

// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>



/ {

	soc {

		dsp_wdt: watchdog@1700400 {

			compatible = "allwinner,sun20i-d1-wdt";

			reg = <0x1700400 0x20>;

			interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dcxo>, <&rtc CLK_OSC32K>;

			clock-names = "hosc", "losc";

			status = "reserved";

		};

	};

};

arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

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