Commit 0913507c authored by Gaël PORTAY's avatar Gaël PORTAY Committed by Chanwoo Choi
Browse files

dt-bindings: devfreq: rk3399_dmc: Remove references of unexistant defines 



Those DDR related defines do not exist. Replace their references with
their numerical constant.

Signed-off-by: default avatarGaël PORTAY <gael.portay@collabora.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
parent 62467a84

Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

+34 −39
Original line number Diff line number Diff line
@@ -79,24 +79,23 @@ Following properties relate to DDR timing: 


- rockchip,ddr3_drv :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is DDR3_DS_40ohm.

				  value is 40.



- rockchip,ddr3_odt :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is DDR3_ODT_120ohm.

				  is 120.



- rockchip,phy_ddr3_ca_drv :	  When the DRAM type is DDR3, this parameter defines

				  the phy side CA line (incluing command line,

				  address line and clock line) driver strength.

				  Default value is PHY_DRV_ODT_40.

				  Default value is 40.



- rockchip,phy_ddr3_dq_drv :	  When the DRAM type is DDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is PHY_DRV_ODT_40.

				  driver strength. Default value is 40.



- rockchip,phy_ddr3_odt : 	  When the DRAM type is DDR3, this parameter defines

				  the PHY side ODT strength. Default value is

				  PHY_DRV_ODT_240.

				  the PHY side ODT strength. Default value is 240.



- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines

				  then ODT disable frequency in MHz (Mega Hz).
@@ -106,25 +105,23 @@ Following properties relate to DDR timing: 


- rockchip,lpddr3_drv :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is LP3_DS_34ohm.

				  value is 34.



- rockchip,lpddr3_odt :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is LP3_ODT_240ohm.

				  is 240.



- rockchip,phy_lpddr3_ca_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side CA line (including command line,

				  address line and clock line) driver strength.

				  Default value is PHY_DRV_ODT_40.

				  Default value is 40.



- rockchip,phy_lpddr3_dq_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is

				  PHY_DRV_ODT_40.

				  driver strength. Default value is 40.



- rockchip,phy_lpddr3_odt : 	  When dram type is LPDDR3, this parameter define

				  the phy side odt strength, default value is

				  PHY_DRV_ODT_240.

				  the phy side odt strength, default value is 240.



- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter

				  defines the ODT disable frequency in
@@ -134,32 +131,30 @@ Following properties relate to DDR timing: 


- rockchip,lpddr4_drv :		  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is LP4_PDDS_60ohm.

				  value is 60.



- rockchip,lpddr4_dq_odt : 	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on DQS/DQ line strength in ohms.

				  Default value is LP4_DQ_ODT_40ohm.

				  Default value is 40.



- rockchip,lpddr4_ca_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on CA line strength in ohms.

				  Default value is LP4_CA_ODT_40ohm.

				  Default value is 40.



- rockchip,phy_lpddr4_ca_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side CA line (including command address

				  line) driver strength. Default value is

				  PHY_DRV_ODT_40.

				  line) driver strength. Default value is 40.



- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines

				  the PHY side clock line and CS line driver

				  strength. Default value is PHY_DRV_ODT_80.

				  strength. Default value is 80.



- rockchip,phy_lpddr4_dq_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is PHY_DRV_ODT_80.

				  driver strength. Default value is 80.



- rockchip,phy_lpddr4_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side ODT strength. Default value is

				  PHY_DRV_ODT_60.

				  the PHY side ODT strength. Default value is 60.



Example:

	dmc_opp_table: dmc_opp_table {
@@ -195,23 +190,23 @@ Example: 
		rockchip,phy_dll_dis_freq = <125>;

		rockchip,auto_pd_dis_freq = <666>;

		rockchip,ddr3_odt_dis_freq = <333>;

		rockchip,ddr3_drv = <DDR3_DS_40ohm>;

		rockchip,ddr3_odt = <DDR3_ODT_120ohm>;

		rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;

		rockchip,ddr3_drv = <40>;

		rockchip,ddr3_odt = <120>;

		rockchip,phy_ddr3_ca_drv = <40>;

		rockchip,phy_ddr3_dq_drv = <40>;

		rockchip,phy_ddr3_odt = <240>;

		rockchip,lpddr3_odt_dis_freq = <333>;

		rockchip,lpddr3_drv = <LP3_DS_34ohm>;

		rockchip,lpddr3_odt = <LP3_ODT_240ohm>;

		rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;

		rockchip,lpddr3_drv = <34>;

		rockchip,lpddr3_odt = <240>;

		rockchip,phy_lpddr3_ca_drv = <40>;

		rockchip,phy_lpddr3_dq_drv = <40>;

		rockchip,phy_lpddr3_odt = <240>;

		rockchip,lpddr4_odt_dis_freq = <333>;

		rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;

		rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;

		rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;

		rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;

		rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;

		rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;

		rockchip,lpddr4_drv = <60>;

		rockchip,lpddr4_dq_odt = <40>;

		rockchip,lpddr4_ca_odt = <40>;

		rockchip,phy_lpddr4_ca_drv = <40>;

		rockchip,phy_lpddr4_ck_cs_drv = <80>;

		rockchip,phy_lpddr4_dq_drv = <80>;

		rockchip,phy_lpddr4_odt = <60>;

	};