Commit 0a42a37f authored by Muralidhara M K's avatar Muralidhara M K Committed by Borislav Petkov (AMD)
Browse files

EDAC/amd64: Split setup_mci_misc_attrs() into dct/umc functions 



The init_one_instance() path is shared between legacy and modern
systems. So add the new functions to a function pointer in pvt->ops.

No functional change is intended.

  [ Yazen: Rebased/reworked patch and reworded commit message. ]

Signed-off-by: default avatarMuralidhara M K <muralidhara.mk@amd.com>
Co-developed-by: default avatarNaveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Signed-off-by: default avatarNaveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Co-developed-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-18-yazen.ghannam@amd.com
parent eb2bcdfc

drivers/edac/amd64_edac.c

+24 −13
Original line number Diff line number Diff line
@@ -3616,22 +3616,18 @@ f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) 
	}

}



static void setup_mci_misc_attrs(struct mem_ctl_info *mci)

static void dct_setup_mci_misc_attrs(struct mem_ctl_info *mci)

{

	struct amd64_pvt *pvt = mci->pvt_info;



	mci->mtype_cap		= MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;

	mci->edac_ctl_cap	= EDAC_FLAG_NONE;



	if (pvt->umc) {

		f17h_determine_edac_ctl_cap(mci, pvt);

	} else {

	if (pvt->nbcap & NBCAP_SECDED)

		mci->edac_ctl_cap |= EDAC_FLAG_SECDED;



	if (pvt->nbcap & NBCAP_CHIPKILL)

		mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;

	}



	mci->edac_cap		= determine_edac_cap(pvt);

	mci->mod_name		= EDAC_MOD_STR;
@@ -3639,14 +3635,27 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) 
	mci->dev_name		= pci_name(pvt->F3);

	mci->ctl_page_to_phys	= NULL;



	if (pvt->fam >= 0x17)

		return;



	/* memory scrubber interface */

	mci->set_sdram_scrub_rate = set_scrub_rate;

	mci->get_sdram_scrub_rate = get_scrub_rate;

}



static void umc_setup_mci_misc_attrs(struct mem_ctl_info *mci)

{

	struct amd64_pvt *pvt = mci->pvt_info;



	mci->mtype_cap		= MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;

	mci->edac_ctl_cap	= EDAC_FLAG_NONE;



	f17h_determine_edac_ctl_cap(mci, pvt);



	mci->edac_cap		= determine_edac_cap(pvt);

	mci->mod_name		= EDAC_MOD_STR;

	mci->ctl_name		= pvt->ctl_name;

	mci->dev_name		= pci_name(pvt->F3);

	mci->ctl_page_to_phys	= NULL;

}



static int dct_hw_info_get(struct amd64_pvt *pvt)

{

	int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id);
@@ -3686,6 +3695,7 @@ static void hw_info_put(struct amd64_pvt *pvt) 
static struct low_ops umc_ops = {

	.hw_info_get			= umc_hw_info_get,

	.ecc_enabled			= umc_ecc_enabled,

	.setup_mci_misc_attrs		= umc_setup_mci_misc_attrs,

};



/* Use Family 16h versions for defaults and adjust as needed below. */
@@ -3694,6 +3704,7 @@ static struct low_ops dct_ops = { 
	.dbam_to_cs			= f16_dbam_to_chip_select,

	.hw_info_get			= dct_hw_info_get,

	.ecc_enabled			= dct_ecc_enabled,

	.setup_mci_misc_attrs		= dct_setup_mci_misc_attrs,

};



static int per_family_init(struct amd64_pvt *pvt)
@@ -3856,7 +3867,7 @@ static int init_one_instance(struct amd64_pvt *pvt) 
	mci->pvt_info = pvt;

	mci->pdev = &pvt->F3->dev;



	setup_mci_misc_attrs(mci);

	pvt->ops->setup_mci_misc_attrs(mci);



	if (init_csrows(mci))

		mci->edac_cap = EDAC_FLAG_NONE;

drivers/edac/amd64_edac.h

+1 −0
Original line number Diff line number Diff line
@@ -468,6 +468,7 @@ struct low_ops { 
			   unsigned int cs_mode, int cs_mask_nr);

	int (*hw_info_get)(struct amd64_pvt *pvt);

	bool (*ecc_enabled)(struct amd64_pvt *pvt);

	void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);

};



int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,