Commit 0a930f64 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a774a1: Add missing assigned-clocks for CAN[01] 



Define "assigned-clocks" and "assigned-clock-rates" properties
for CAN[01] DT nodes, as required by the dt-bindings.

Fixes: eccc4000 ("arm64: dts: renesas: r8a774a1: Add clkp2 clock to CAN nodes")
Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: default avatarChris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e8efd2a8

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -1128,6 +1128,8 @@ can0: can@e6c30000 { 
				 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,

				 <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 916>;

			status = "disabled";
@@ -1142,6 +1144,8 @@ can1: can@e6c38000 { 
				 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,

				 <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

			resets = <&cpg 915>;

			status = "disabled";