Unverified Commit 0b066a68 authored by Tim Gover's avatar Tim Gover Committed by Maxime Ripard
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drm: vc4: Fix pixel-wrap issue with DVP teardown 



Adjust the DVP enable/disable sequence to avoid a pixel getting stuck
in an internal, non resettable FIFO within PixelValve when changing
HDMI resolution.

The blank pixels features of the DVP can prevent signals back to
pixelvalve causing it to not clear the FIFO. Adjust the ordering
and timing of operations to ensure the clear signal makes it through to
pixelvalve.

Signed-off-by: default avatarTim Gover <tim.gover@raspberrypi.com>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20210628130533.144617-1-maxime@cerno.tech
parent 9d9fb756

drivers/gpu/drm/vc4/vc4_hdmi.c

+8 −7
Original line number Diff line number Diff line
@@ -605,12 +605,12 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 


	HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);



	HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |

		   VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);

	HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);



	HDMI_WRITE(HDMI_VID_CTL,

		   HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);

	mdelay(1);



	HDMI_WRITE(HDMI_VID_CTL,

		   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);

	vc4_hdmi_disable_scrambling(encoder);

}
@@ -620,12 +620,12 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 
	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);

	int ret;



	HDMI_WRITE(HDMI_VID_CTL,

		   HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);



	if (vc4_hdmi->variant->phy_disable)

		vc4_hdmi->variant->phy_disable(vc4_hdmi);



	HDMI_WRITE(HDMI_VID_CTL,

		   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);



	clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);

	clk_disable_unprepare(vc4_hdmi->hsm_clock);

	clk_disable_unprepare(vc4_hdmi->pixel_clock);
@@ -1017,6 +1017,7 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 


	HDMI_WRITE(HDMI_VID_CTL,

		   VC4_HD_VID_CTL_ENABLE |

		   VC4_HD_VID_CTL_CLRRGB |

		   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |

		   VC4_HD_VID_CTL_FRAME_COUNTER_RESET |

		   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |