Commit 0c1356e0 authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Shawn Guo
Browse files

ARM: dts: imx7-colibri: clean-up usdhc1 and add sleep config 



Adding no-1-8-v property to usdhc1 to disable +1.8V signaling (UHS-I)
mode on SoM dtsi level.

Clean up no-1-8-v from Aster carrier board dtsi, which is using defaults
from SoM dtsi and is not UHS-I capable.

A carrier board may have a MMC/SD card slot with a switchable power
supply. Add a pinctrl sleep used when the card power is off to avoid
backfeeding to the card and add the "sleep" pinctrl to the usdhc1
controller.

Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent fe20bfa5

arch/arm/boot/dts/imx7-colibri-aster.dtsi

+1 −4
Original line number Diff line number Diff line
@@ -61,10 +61,7 @@ &usbotg1 { 
	status = "okay";

};



/* Colibri MMC/SD */

&usdhc1 {

	keep-power-in-suspend;

	no-1-8-v;

	wakeup-source;

	vmmc-supply = <&reg_3v3>;

	status = "okay";

};

arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi

+0 −3
Original line number Diff line number Diff line
@@ -97,8 +97,5 @@ &usbotg1 { 
};



&usdhc1 {

	keep-power-in-suspend;

	wakeup-source;

	vmmc-supply = <&reg_3v3>;

	status = "okay";

};

arch/arm/boot/dts/imx7-colibri.dtsi

+50 −25
Original line number Diff line number Diff line
@@ -585,12 +585,19 @@ &usbotg1 { 
	extcon = <0>, <&extcon_usbc_det>;

};



/* Colibri MMC/SD */

&usdhc1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;

	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;

	disable-wp;

	no-1-8-v;

	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";

	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;

	pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;

	pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;

	pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>;

	vmmc-supply = <&reg_3v3>;

	vqmmc-supply = <&reg_LDO2>;

	wakeup-source;

};



&usdhc3 {
@@ -949,21 +956,21 @@ MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ 
		>;

	};



	pinctrl_usdhc1: usdhc1-grp {

	pinctrl_usdhc1: usdhc1grp {

		fsl,pins = <

			MX7D_PAD_SD1_CMD__SD1_CMD	0x59

			MX7D_PAD_SD1_CLK__SD1_CLK	0x19

			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59

			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59

			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59

			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59

			MX7D_PAD_SD1_CLK__SD1_CLK		0x19 /* SODIMM 47 */

			MX7D_PAD_SD1_CMD__SD1_CMD		0x59 /* SODIMM 190 */

			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59 /* SODIMM 192 */

			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59 /* SODIMM 49 */

			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59 /* SODIMM 51 */

			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59 /* SODIMM 53 */

		>;

	};



	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {

		fsl,pins = <

			MX7D_PAD_SD1_CMD__SD1_CMD	0x5a

			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a

			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a

			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a

			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a

			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
@@ -971,10 +978,10 @@ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a 
		>;

	};



	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {

		fsl,pins = <

			MX7D_PAD_SD1_CMD__SD1_CMD	0x5b

			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b

			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b

			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b

			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b

			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
@@ -982,6 +989,18 @@ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b 
		>;

	};



	/* Avoid backfeeding with removed card power. */

	pinctrl_usdhc1_sleep: usdhc1-slpgrp {

		fsl,pins = <

			MX7D_PAD_SD1_CMD__SD1_CMD		0x10

			MX7D_PAD_SD1_CLK__SD1_CLK		0x10

			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x10

			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x10

			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x10

			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x10

		>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <

			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
@@ -1077,9 +1096,15 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f 
		>;

	};



	pinctrl_cd_usdhc1: usdhc1-cd-grp {

	pinctrl_cd_usdhc1: cdusdhc1grp {

		fsl,pins = <

			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* SODIMM 43 / MMC_CD */

		>;

	};



	pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp {

		fsl,pins = <

			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* CD */

			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x0

		>;

	};