Commit 0cfa43ab authored by Swapnil Jakhade's avatar Swapnil Jakhade Committed by Vinod Koul
Browse files

phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration 



Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.

Signed-off-by: default avatarSwapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: default avatarRoger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 45810d48

drivers/phy/cadence/phy-cadence-sierra.c

+139 −2
Original line number Original line Diff line number Diff line
@@ -24,7 +24,7 @@ 
#include <dt-bindings/phy/phy-cadence.h>

#include <dt-bindings/phy/phy-cadence.h>





#define NUM_SSC_MODE		3

#define NUM_SSC_MODE		3

#define NUM_PHY_TYPE		4

#define NUM_PHY_TYPE		5





/* PHY register offsets */

/* PHY register offsets */

#define SIERRA_COMMON_CDB_OFFSET			0x0

#define SIERRA_COMMON_CDB_OFFSET			0x0
@@ -46,7 +46,9 @@ 
#define SIERRA_CMN_REFRCV_PREG				0x98

#define SIERRA_CMN_REFRCV_PREG				0x98

#define SIERRA_CMN_REFRCV1_PREG				0xB8

#define SIERRA_CMN_REFRCV1_PREG				0xB8

#define SIERRA_CMN_PLLLC1_GEN_PREG			0xC2

#define SIERRA_CMN_PLLLC1_GEN_PREG			0xC2

#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG		0xC3

#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG		0xCA

#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG		0xCA

#define SIERRA_CMN_PLLLC1_CLK0_PREG			0xCE

#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG		0xD0

#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG		0xD0

#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG	0xE2

#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG	0xE2
@@ -74,6 +76,7 @@ 
#define SIERRA_PSC_RX_A1_PREG				0x031

#define SIERRA_PSC_RX_A1_PREG				0x031

#define SIERRA_PSC_RX_A2_PREG				0x032

#define SIERRA_PSC_RX_A2_PREG				0x032

#define SIERRA_PSC_RX_A3_PREG				0x033

#define SIERRA_PSC_RX_A3_PREG				0x033

#define SIERRA_PLLCTRL_FBDIV_MODE01_PREG		0x039

#define SIERRA_PLLCTRL_SUBRATE_PREG			0x03A

#define SIERRA_PLLCTRL_SUBRATE_PREG			0x03A

#define SIERRA_PLLCTRL_GEN_A_PREG			0x03B

#define SIERRA_PLLCTRL_GEN_A_PREG			0x03B

#define SIERRA_PLLCTRL_GEN_D_PREG			0x03E

#define SIERRA_PLLCTRL_GEN_D_PREG			0x03E
@@ -305,6 +308,7 @@ enum cdns_sierra_phy_type { 
	TYPE_NONE,

	TYPE_NONE,

	TYPE_PCIE,

	TYPE_PCIE,

	TYPE_USB,

	TYPE_USB,

	TYPE_SGMII,

	TYPE_QSGMII

	TYPE_QSGMII

};

};
@@ -929,6 +933,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 
	case PHY_TYPE_USB3:

	case PHY_TYPE_USB3:

		inst->phy_type = TYPE_USB;

		inst->phy_type = TYPE_USB;

		break;

		break;

	case PHY_TYPE_SGMII:

		inst->phy_type = TYPE_SGMII;

		break;

	case PHY_TYPE_QSGMII:

	case PHY_TYPE_QSGMII:

		inst->phy_type = TYPE_QSGMII;

		inst->phy_type = TYPE_QSGMII;

		break;

		break;
@@ -1316,7 +1323,7 @@ static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) 
			}

			}

		}

		}





		if (phy_t1 == TYPE_QSGMII)

		if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII)

			reset_control_deassert(sp->phys[node].lnk_rst);

			reset_control_deassert(sp->phys[node].lnk_rst);

	}

	}
@@ -1514,6 +1521,71 @@ static void cdns_sierra_phy_remove(struct platform_device *pdev) 
	cdns_sierra_clk_unregister(phy);

	cdns_sierra_clk_unregister(phy);

}

}





/* SGMII PHY PMA lane configuration */

static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = {

	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}

};



static struct cdns_sierra_vals sgmii_phy_pma_ln_vals = {

	.reg_pairs = sgmii_phy_pma_ln_regs,

	.num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs),

};



/* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */

static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = {

	{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},

	{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},

	{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},

	{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},

	{0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}

};



static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = {

	{0x688E, SIERRA_DET_STANDEC_D_PREG},

	{0x0004, SIERRA_PSC_LN_IDLE_PREG},

	{0x0FFE, SIERRA_PSC_RX_A0_PREG},

	{0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},

	{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},

	{0x0003, SIERRA_PLLCTRL_GEN_A_PREG},

	{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},

	{0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG },

	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},

	{0x9702, SIERRA_DRVCTRL_BOOST_PREG},

	{0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},

	{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},

	{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},

	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},

	{0x0002, SIERRA_DEQ_PHALIGN_CTRL},

	{0x0186, SIERRA_DEQ_GLUT0},

	{0x0186, SIERRA_DEQ_GLUT1},

	{0x0186, SIERRA_DEQ_GLUT2},

	{0x0186, SIERRA_DEQ_GLUT3},

	{0x0186, SIERRA_DEQ_GLUT4},

	{0x0861, SIERRA_DEQ_ALUT0},

	{0x07E0, SIERRA_DEQ_ALUT1},

	{0x079E, SIERRA_DEQ_ALUT2},

	{0x071D, SIERRA_DEQ_ALUT3},

	{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},

	{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},

	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0033, SIERRA_DEQ_PICTRL_PREG},

	{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},

	{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},

	{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},

	{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}

};



static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = {

	.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs,

	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs),

};



static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = {

	.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs,

	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs),

};



/* QSGMII PHY PMA lane configuration */

/* QSGMII PHY PMA lane configuration */

static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {

static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {

	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}

	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
@@ -2340,6 +2412,11 @@ static const struct cdns_sierra_data cdns_map_sierra = { 
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

			},

			},

			[TYPE_SGMII] = {

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

			},

			[TYPE_QSGMII] = {

			[TYPE_QSGMII] = {

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
@@ -2354,6 +2431,11 @@ static const struct cdns_sierra_data cdns_map_sierra = { 
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,

			},

			},

			[TYPE_SGMII] = {

				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,

			},

			[TYPE_QSGMII] = {

			[TYPE_QSGMII] = {

				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,

				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
@@ -2365,6 +2447,13 @@ static const struct cdns_sierra_data cdns_map_sierra = { 
				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,

				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,

			},

			},

		},

		},

		[TYPE_SGMII] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,

				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,

				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,

			},

		},

		[TYPE_QSGMII] = {

		[TYPE_QSGMII] = {

			[TYPE_PCIE] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
@@ -2380,6 +2469,11 @@ static const struct cdns_sierra_data cdns_map_sierra = { 
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,

			},

			},

			[TYPE_SGMII] = {

				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,

				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,

				[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,

			},

			[TYPE_QSGMII] = {

			[TYPE_QSGMII] = {

				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,

				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,

				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,

				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
@@ -2391,6 +2485,13 @@ static const struct cdns_sierra_data cdns_map_sierra = { 
				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,

				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,

			},

			},

		},

		},

		[TYPE_SGMII] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,

				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,

				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,

			},

		},

		[TYPE_QSGMII] = {

		[TYPE_QSGMII] = {

			[TYPE_PCIE] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
@@ -2412,6 +2513,11 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

			},

			},

			[TYPE_SGMII] = {

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

			},

			[TYPE_QSGMII] = {

			[TYPE_QSGMII] = {

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
@@ -2420,6 +2526,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
		},

		},

	},

	},

	.phy_pma_ln_vals = {

	.phy_pma_ln_vals = {

		[TYPE_SGMII] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &sgmii_phy_pma_ln_vals,

				[EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals,

				[INTERNAL_SSC] = &sgmii_phy_pma_ln_vals,

			},

		},

		[TYPE_QSGMII] = {

		[TYPE_QSGMII] = {

			[TYPE_PCIE] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &qsgmii_phy_pma_ln_vals,

				[NO_SSC] = &qsgmii_phy_pma_ln_vals,
@@ -2435,6 +2548,11 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,

			},

			},

			[TYPE_SGMII] = {

				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,

			},

			[TYPE_QSGMII] = {

			[TYPE_QSGMII] = {

				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,

				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
@@ -2446,6 +2564,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,

				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,

			},

			},

		},

		},

		[TYPE_SGMII] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,

				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,

				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,

			},

		},

		[TYPE_QSGMII] = {

		[TYPE_QSGMII] = {

			[TYPE_PCIE] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
@@ -2461,6 +2586,11 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,

			},

			},

			[TYPE_SGMII] = {

				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,

				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,

				[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,

			},

			[TYPE_QSGMII] = {

			[TYPE_QSGMII] = {

				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,

				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,

				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,

				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
@@ -2472,6 +2602,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,

				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,

			},

			},

		},

		},

		[TYPE_SGMII] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,

				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,

				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,

			},

		},

		[TYPE_QSGMII] = {

		[TYPE_QSGMII] = {

			[TYPE_PCIE] = {

			[TYPE_PCIE] = {

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,

				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,