Commit 0d1b10c6 authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets 



Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information.  Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.

changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- re arrange sc8280xp_dsc[]

changes in v4:
-- fix checkpatch warning

changes in v10:
-- remove hard slice from commit text
-- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN
-- change DSC_BLK_1_2 .len from 0x100 to 0x29c

changes in v11:
-- remove comment at DSC_BLK_1_2 marco

Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarKuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/539507/
Link: https://lore.kernel.org/r/1685036458-22683-10-git-send-email-quic_khsieh@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 8c4094b2

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

+14 −0
Original line number Diff line number Diff line
@@ -153,6 +153,18 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { 
	MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),

};



/*

 * NOTE: Each display compression engine (DCE) contains dual hard

 * slice DSC encoders so both share same base address but with

 * its own different sub block address.

 */

static const struct dpu_dsc_cfg sm8350_dsc[] = {

	DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),

	DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),

	DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),

	DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),

};



static const struct dpu_intf_cfg sm8350_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -215,6 +227,8 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = { 
	.dspp = sm8350_dspp,

	.pingpong_count = ARRAY_SIZE(sm8350_pp),

	.pingpong = sm8350_pp,

	.dsc_count = ARRAY_SIZE(sm8350_dsc),

	.dsc = sm8350_dsc,

	.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),

	.merge_3d = sm8350_merge_3d,

	.intf_count = ARRAY_SIZE(sm8350_intf),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

+7 −0
Original line number Diff line number Diff line
@@ -94,6 +94,11 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { 
	PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),

};



/* NOTE: sc7280 only has one DSC hard slice encoder */

static const struct dpu_dsc_cfg sc7280_dsc[] = {

	DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),

};



static const struct dpu_wb_cfg sc7280_wb[] = {

	WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,

			VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
@@ -155,6 +160,8 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = { 
	.mixer = sc7280_lm,

	.pingpong_count = ARRAY_SIZE(sc7280_pp),

	.pingpong = sc7280_pp,

	.dsc_count = ARRAY_SIZE(sc7280_dsc),

	.dsc = sc7280_dsc,

	.wb_count = ARRAY_SIZE(sc7280_wb),

	.wb = sc7280_wb,

	.intf_count = ARRAY_SIZE(sc7280_intf),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

+16 −0
Original line number Diff line number Diff line
@@ -142,6 +142,20 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { 
	MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),

};



/*

 * NOTE: Each display compression engine (DCE) contains dual hard

 * slice DSC encoders so both share same base address but with

 * its own different sub block address.

 */

static const struct dpu_dsc_cfg sc8280xp_dsc[] = {

	DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),

	DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),

	DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),

	DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),

	DSC_BLK_1_2("dce_2_0", DSC_4, 0x82000, 0x29c, 0, dsc_sblk_0),

	DSC_BLK_1_2("dce_2_1", DSC_5, 0x82000, 0x29c, 0, dsc_sblk_1),

};



/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */

static const struct dpu_intf_cfg sc8280xp_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
@@ -217,6 +231,8 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { 
	.dspp = sc8280xp_dspp,

	.pingpong_count = ARRAY_SIZE(sc8280xp_pp),

	.pingpong = sc8280xp_pp,

	.dsc_count = ARRAY_SIZE(sc8280xp_dsc),

	.dsc = sc8280xp_dsc,

	.merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d),

	.merge_3d = sc8280xp_merge_3d,

	.intf_count = ARRAY_SIZE(sc8280xp_intf),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

+14 −0
Original line number Diff line number Diff line
@@ -161,6 +161,18 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { 
	MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),

};



/*

 * NOTE: Each display compression engine (DCE) contains dual hard

 * slice DSC encoders so both share same base address but with

 * its own different sub block address.

 */

static const struct dpu_dsc_cfg sm8450_dsc[] = {

	DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),

	DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),

	DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),

	DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),

};



static const struct dpu_intf_cfg sm8450_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -223,6 +235,8 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = { 
	.dspp = sm8450_dspp,

	.pingpong_count = ARRAY_SIZE(sm8450_pp),

	.pingpong = sm8450_pp,

	.dsc_count = ARRAY_SIZE(sm8450_dsc),

	.dsc = sm8450_dsc,

	.merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),

	.merge_3d = sm8450_merge_3d,

	.intf_count = ARRAY_SIZE(sm8450_intf),

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

+14 −0
Original line number Diff line number Diff line
@@ -165,6 +165,18 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 
	MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),

};



/*

 * NOTE: Each display compression engine (DCE) contains dual hard

 * slice DSC encoders so both share same base address but with

 * its own different sub block address.

 */

static const struct dpu_dsc_cfg sm8550_dsc[] = {

	DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),

	DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),

	DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),

	DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),

};



static const struct dpu_intf_cfg sm8550_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -227,6 +239,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { 
	.dspp = sm8550_dspp,

	.pingpong_count = ARRAY_SIZE(sm8550_pp),

	.pingpong = sm8550_pp,

	.dsc_count = ARRAY_SIZE(sm8550_dsc),

	.dsc = sm8550_dsc,

	.merge_3d_count = ARRAY_SIZE(sm8550_merge_3d),

	.merge_3d = sm8550_merge_3d,

	.intf_count = ARRAY_SIZE(sm8550_intf),