Commit 0e2b014e authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Thierry Reding
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dt-bindings: Add headers for NVDEC on Tegra234 



Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.

Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 9abf2313

include/dt-bindings/clock/tegra234-clock.h

+4 −0
Original line number Diff line number Diff line
@@ -82,6 +82,8 @@ 
#define TEGRA234_CLK_I2S6			66U

/** @brief clock recovered from I2S6 input */

#define TEGRA234_CLK_I2S6_SYNC_INPUT		67U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */

#define TEGRA234_CLK_NVDEC			83U

/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */

#define TEGRA234_CLK_PLLA			93U

/** @brief PLLP clk output */
@@ -130,6 +132,8 @@ 
#define TEGRA234_CLK_SYNC_I2S5			149U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */

#define TEGRA234_CLK_SYNC_I2S6			150U

/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */

#define TEGRA234_CLK_TSEC_PKA			154U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */

#define TEGRA234_CLK_UARTA			155U

/** @brief output of gate CLK_ENB_PEX1_CORE_6 */

include/dt-bindings/memory/tegra234-mc.h

+3 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#define TEGRA234_SID_PCIE10	0x0b

#define TEGRA234_SID_BPMP	0x10

#define TEGRA234_SID_HOST1X	0x27

#define TEGRA234_SID_NVDEC	0x29

#define TEGRA234_SID_VIC	0x34



/* Shared stream IDs */
@@ -101,6 +102,8 @@ 
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67

#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c

#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d

#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78

#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79

/* BPMP read client */

#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93

/* BPMP write client */

include/dt-bindings/power/tegra234-powergate.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define TEGRA234_POWER_DOMAIN_MGBEB	18U

#define TEGRA234_POWER_DOMAIN_MGBEC	19U

#define TEGRA234_POWER_DOMAIN_MGBED	20U

#define TEGRA234_POWER_DOMAIN_NVDEC	23U

#define TEGRA234_POWER_DOMAIN_VIC	29U



#endif

include/dt-bindings/reset/tegra234-reset.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#define TEGRA234_RESET_I2C7			33U

#define TEGRA234_RESET_I2C8			34U

#define TEGRA234_RESET_I2C9			35U

#define TEGRA234_RESET_NVDEC			44U

#define TEGRA234_RESET_MGBE0_PCS		45U

#define TEGRA234_RESET_MGBE0_MAC		46U

#define TEGRA234_RESET_MGBE1_PCS		49U