Commit 0ec15b6f authored by Kaushal Kumar's avatar Kaushal Kumar Committed by Bjorn Andersson
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ARM: dts: qcom: sdx65: Add QPIC NAND support 



Add devicetree node to enable support for QPIC
NAND controller on Qualcomm SDX65 platform.
Since there is no "aon" clock in SDX65, a dummy
clock is provided.

Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarKaushal Kumar <quic_kaushalk@quicinc.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651511286-18690-3-git-send-email-quic_kaushalk@quicinc.com
parent ab11b74d

arch/arm/boot/dts/qcom-sdx65.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -37,6 +37,12 @@ sleep_clk: sleep-clk { 
			clock-output-names = "sleep_clk";

			#clock-cells = <0>;

		};



		nand_clk_dummy: nand-clk-dummy {

			compatible = "fixed-clock";

			clock-frequency = <32764>;

			#clock-cells = <0>;

		};

	};



	cpus {
@@ -204,6 +210,22 @@ qpic_bam: dma-controller@1b04000 { 
			status = "disabled";

		};



		qpic_nand: nand-controller@1b30000 {

			compatible = "qcom,sdx55-nand";

			reg = <0x01b30000 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&rpmhcc RPMH_QPIC_CLK>,

				 <&nand_clk_dummy>;

			clock-names = "core", "aon";



			dmas = <&qpic_bam 0>,

			       <&qpic_bam 1>,

			       <&qpic_bam 2>;

			dma-names = "tx", "rx", "cmd";

			status = "disabled";

		};



		tcsr_mutex: hwlock@1f40000 {

			compatible = "qcom,tcsr-mutex";

			reg = <0x01f40000 0x40000>;