Commit 0f31f62d authored by Erik Andrén's avatar Erik Andrén Committed by Greg Kroah-Hartman
Browse files

Staging: agnx: Fixup phy.c checkpatch warnings 



Signed-off-by: default avatarErik Andrén <erik.andren@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent f58e12e4

drivers/staging/agnx/phy.c

+16 −16
Original line number Diff line number Diff line
@@ -401,9 +401,9 @@ static void rx_management_init(struct agnx_priv *priv) 
		agnx_write32(ctl, 0x2074, 0x1f171710);

		agnx_write32(ctl, 0x2078, 0x10100d0d);

		agnx_write32(ctl, 0x207c, 0x11111010);

	}

	else

	} else {

		agnx_write32(ctl, AGNX_RXM_DELAY11, 0x0);

	}

	agnx_write32(ctl, AGNX_RXM_REQRATE, 0x8195e00);

}
@@ -476,7 +476,7 @@ static void gain_ctlcnt_init(struct agnx_priv *priv) 
	/* It seemed if we set other bit to 1 the bit 0 will

	   be auto change to 0 */

	agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x2 | 0x1);

//	agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x1);

/*	agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x1); */

} /* gain_ctlcnt_init */
@@ -586,7 +586,7 @@ static void phy_init(struct agnx_priv *priv) 
		agnx_write32(ctl, AGNX_GCR_SIFST11B, 0x28);

		agnx_write32(ctl, AGNX_GCR_CWDETEC, 0x0);

		agnx_write32(ctl, AGNX_GCR_0X38, 0x1e);

//		agnx_write32(ctl, AGNX_GCR_BOACT, 0x26);

/*		agnx_write32(ctl, AGNX_GCR_BOACT, 0x26);*/

		agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);



		agnx_write32(ctl, AGNX_GCR_THCAP11A, 0x32);
@@ -882,11 +882,11 @@ static void card_interface_init(struct agnx_priv *priv) 


	/* FIXME Set to managed mode */

	set_managed_mode(priv);

//	set_promiscuous_mode(priv);

/*	set_promiscuous_mode(priv); */

/*	set_scan_mode(priv); */

/*	set_learn_mode(priv); */

// 	set_promis_and_managed(priv);

// 	set_adhoc_mode(priv);

/*	set_promis_and_managed(priv); */

/*	set_adhoc_mode(priv); */



	/* Set the recieve request rate */

	/* Check packet length */