Commit 0f69a423 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
Browse files

clk: mediatek: Switch to mtk_clk_simple_probe() where possible 



mtk_clk_simple_probe() is a function that registers mtk gate clocks
and, if reset data is present, a reset controller and across all of
the MTK clock drivers, such a function is duplicated many times:
switch to the common mtk_clk_simple_probe() function for all of the
clock drivers that are registering as platform drivers.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarMiles Chen <miles.chen@mediatek.com>
Tested-by: default avatarMiles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com


Tested-by: default avatarMingming Su <mingming.su@mediatek.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 4c02c9af

drivers/clk/mediatek/clk-mt2701-aud.c

+18 −13
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ static const struct mtk_gate_regs audio3_cg_regs = { 
};



static const struct mtk_gate audio_clks[] = {

	GATE_DUMMY(CLK_DUMMY, "aud_dummy"),

	/* AUDIO0 */

	GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),

	GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
@@ -138,29 +139,27 @@ static const struct mtk_gate audio_clks[] = { 
	GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),

};



static const struct mtk_clk_desc audio_desc = {

	.clks = audio_clks,

	.num_clks = ARRAY_SIZE(audio_clks),

};



static const struct of_device_id of_match_clk_mt2701_aud[] = {

	{ .compatible = "mediatek,mt2701-audsys", },

	{}

	{ .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },

	{ /* sentinel */ }

};



static int clk_mt2701_aud_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	struct device_node *node = pdev->dev.of_node;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);



	mtk_clk_register_gates(&pdev->dev, node, audio_clks,

			       ARRAY_SIZE(audio_clks), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	r = mtk_clk_simple_probe(pdev);

	if (r) {

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);



		goto err_clk_provider;

		return r;

	}



	r = devm_of_platform_populate(&pdev->dev);
@@ -170,13 +169,19 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev) 
	return 0;



err_plat_populate:

	of_clk_del_provider(node);

err_clk_provider:

	mtk_clk_simple_remove(pdev);

	return r;

}



static int clk_mt2701_aud_remove(struct platform_device *pdev)

{

	of_platform_depopulate(&pdev->dev);

	return mtk_clk_simple_remove(pdev);

}



static struct platform_driver clk_mt2701_aud_drv = {

	.probe = clk_mt2701_aud_probe,

	.remove = clk_mt2701_aud_remove,

	.driver = {

		.name = "clk-mt2701-aud",

		.of_match_table = of_match_clk_mt2701_aud,

drivers/clk/mediatek/clk-mt2701-eth.c

+11 −25
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ static const struct mtk_gate_regs eth_cg_regs = { 
	}



static const struct mtk_gate eth_clks[] = {

	GATE_DUMMY(CLK_DUMMY, "eth_dummy"),

	GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),

	GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),

	GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
@@ -44,35 +45,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { 
	.rst_bank_nr = ARRAY_SIZE(rst_ofs),

};



static const struct of_device_id of_match_clk_mt2701_eth[] = {

	{ .compatible = "mediatek,mt2701-ethsys", },

	{}

static const struct mtk_clk_desc eth_desc = {

	.clks = eth_clks,

	.num_clks = ARRAY_SIZE(eth_clks),

	.rst_desc = &clk_rst_desc,

};



static int clk_mt2701_eth_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;



	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);



	mtk_clk_register_gates(&pdev->dev, node, eth_clks,

			       ARRAY_SIZE(eth_clks), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r)

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);



	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);



	return r;

}

static const struct of_device_id of_match_clk_mt2701_eth[] = {

	{ .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt2701_eth_drv = {

	.probe = clk_mt2701_eth_probe,

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt2701-eth",

		.of_match_table = of_match_clk_mt2701_eth,

drivers/clk/mediatek/clk-mt2701-g3d.c

+10 −46
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ static const struct mtk_gate_regs g3d_cg_regs = { 
};



static const struct mtk_gate g3d_clks[] = {

	GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),

	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),

};
@@ -43,57 +44,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { 
	.rst_bank_nr = ARRAY_SIZE(rst_ofs),

};



static int clk_mt2701_g3dsys_init(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	struct device_node *node = pdev->dev.of_node;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);



	mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),

			       clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r)

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);



	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);



	return r;

}

static const struct mtk_clk_desc g3d_desc = {

	.clks = g3d_clks,

	.num_clks = ARRAY_SIZE(g3d_clks),

	.rst_desc = &clk_rst_desc,

};



static const struct of_device_id of_match_clk_mt2701_g3d[] = {

	{

		.compatible = "mediatek,mt2701-g3dsys",

		.data = clk_mt2701_g3dsys_init,

	}, {

		/* sentinel */

	}

	{ .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },

	{ /* sentinel */ }

};



static int clk_mt2701_g3d_probe(struct platform_device *pdev)

{

	int (*clk_init)(struct platform_device *);

	int r;



	clk_init = of_device_get_match_data(&pdev->dev);

	if (!clk_init)

		return -EINVAL;



	r = clk_init(pdev);

	if (r)

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);



	return r;

}



static struct platform_driver clk_mt2701_g3d_drv = {

	.probe = clk_mt2701_g3d_probe,

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt2701-g3d",

		.of_match_table = of_match_clk_mt2701_g3d,

drivers/clk/mediatek/clk-mt2701-hif.c

+11 −27
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ static const struct mtk_gate_regs hif_cg_regs = { 
	}



static const struct mtk_gate hif_clks[] = {

	GATE_DUMMY(CLK_DUMMY, "hif_dummy"),

	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),

	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),

	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
@@ -41,37 +42,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { 
	.rst_bank_nr = ARRAY_SIZE(rst_ofs),

};



static const struct of_device_id of_match_clk_mt2701_hif[] = {

	{ .compatible = "mediatek,mt2701-hifsys", },

	{}

static const struct mtk_clk_desc hif_desc = {

	.clks = hif_clks,

	.num_clks = ARRAY_SIZE(hif_clks),

	.rst_desc = &clk_rst_desc,

};



static int clk_mt2701_hif_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;



	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);



	mtk_clk_register_gates(&pdev->dev, node, hif_clks,

			       ARRAY_SIZE(hif_clks), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r) {

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);

		return r;

	}



	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);



	return 0;

}

static const struct of_device_id of_match_clk_mt2701_hif[] = {

	{ .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt2701_hif_drv = {

	.probe = clk_mt2701_hif_probe,

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt2701-hif",

		.of_match_table = of_match_clk_mt2701_hif,

drivers/clk/mediatek/clk-mt2712.c

+32 −51
Original line number Diff line number Diff line
@@ -1363,50 +1363,6 @@ static int clk_mt2712_top_probe(struct platform_device *pdev) 
	return r;

}



static int clk_mt2712_infra_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;



	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);



	mtk_clk_register_gates(&pdev->dev, node, infra_clks,

			       ARRAY_SIZE(infra_clks), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);



	if (r != 0)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);



	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);



	return r;

}



static int clk_mt2712_peri_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;



	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);



	mtk_clk_register_gates(&pdev->dev, node, peri_clks,

			       ARRAY_SIZE(peri_clks), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);



	if (r != 0)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);



	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);



	return r;

}



static int clk_mt2712_mcu_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;
@@ -1444,12 +1400,6 @@ static const struct of_device_id of_match_clk_mt2712[] = { 
	}, {

		.compatible = "mediatek,mt2712-topckgen",

		.data = clk_mt2712_top_probe,

	}, {

		.compatible = "mediatek,mt2712-infracfg",

		.data = clk_mt2712_infra_probe,

	}, {

		.compatible = "mediatek,mt2712-pericfg",

		.data = clk_mt2712_peri_probe,

	}, {

		.compatible = "mediatek,mt2712-mcucfg",

		.data = clk_mt2712_mcu_probe,
@@ -1476,6 +1426,33 @@ static int clk_mt2712_probe(struct platform_device *pdev) 
	return r;

}



static const struct mtk_clk_desc infra_desc = {

	.clks = infra_clks,

	.num_clks = ARRAY_SIZE(infra_clks),

	.rst_desc = &clk_rst_desc[0],

};



static const struct mtk_clk_desc peri_desc = {

	.clks = peri_clks,

	.num_clks = ARRAY_SIZE(peri_clks),

	.rst_desc = &clk_rst_desc[1],

};



static const struct of_device_id of_match_clk_mt2712_simple[] = {

	{ .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },

	{ .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt2712_simple_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt2712-simple",

		.of_match_table = of_match_clk_mt2712_simple,

	},

};



static struct platform_driver clk_mt2712_drv = {

	.probe = clk_mt2712_probe,

	.driver = {
@@ -1486,7 +1463,11 @@ static struct platform_driver clk_mt2712_drv = { 


static int __init clk_mt2712_init(void)

{

	return platform_driver_register(&clk_mt2712_drv);

	int ret = platform_driver_register(&clk_mt2712_drv);



	if (ret)

		return ret;

	return platform_driver_register(&clk_mt2712_simple_drv);

}



arch_initcall(clk_mt2712_init);