Commit 0f6b99d2 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Wei Xu
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arm64: dts: hisilicon: Align UART nodename with dtschema 



Fix dtschema validator warnings like:
    uart@f8015000: $nodename:0: 'uart@f8015000' does not match '^serial(@[0-9a-f,]+)*$'

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 7b8bc95f

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ stub_clock: stub_clock { 
			mboxes = <&mailbox 1 0 11>;

		};



		uart0: uart@f8015000 {	/* console */

		uart0: serial@f8015000 {	/* console */

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xf8015000 0x0 0x1000>;

			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@@ -311,7 +311,7 @@ uart0: uart@f8015000 { /* console */ 
			clock-names = "uartclk", "apb_pclk";

		};



		uart1: uart@f7111000 {

		uart1: serial@f7111000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xf7111000 0x0 0x1000>;

			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -325,7 +325,7 @@ uart1: uart@f7111000 { 
			status = "disabled";

		};



		uart2: uart@f7112000 {

		uart2: serial@f7112000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xf7112000 0x0 0x1000>;

			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -337,7 +337,7 @@ uart2: uart@f7112000 { 
			status = "disabled";

		};



		uart3: uart@f7113000 {

		uart3: serial@f7113000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xf7113000 0x0 0x1000>;

			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
@@ -349,7 +349,7 @@ uart3: uart@f7113000 { 
			status = "disabled";

		};



		uart4: uart@f7114000 {

		uart4: serial@f7114000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xf7114000 0x0 0x1000>;

			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;