Commit 0f6d600a authored by Quinn Tran's avatar Quinn Tran Committed by Martin K. Petersen
Browse files

scsi: qla2xxx: edif: Increase ELS payload

Currently, firmware limits ELS payload to FC frame size/2112.  This patch
adjusts memory buffer size to be able to handle max ELS payload.

Link: https://lore.kernel.org/r/20211026115412.27691-11-njavali@marvell.com


Fixes: 84318a9f ("scsi: qla2xxx: edif: Add send, receive, and accept for auth_els")
Reviewed-by: default avatarHimanshu Madhani <himanshu.madhani@oracle.com>
Signed-off-by: default avatarQuinn Tran <qutran@marvell.com>
Signed-off-by: default avatarNilesh Javali <njavali@marvell.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 91f6f5fb
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+1 −1
Original line number Diff line number Diff line
@@ -2370,7 +2370,7 @@ void qla24xx_auth_els(scsi_qla_host_t *vha, void **pkt, struct rsp_que **rsp)
		return;
	}

	if (totlen > MAX_PAYLOAD) {
	if (totlen > ELS_MAX_PAYLOAD) {
		ql_dbg(ql_dbg_edif, vha, 0x0910d,
		    "%s WARNING: verbose ELS frame received (totlen=%x)\n",
		    __func__, totlen);
+2 −1
Original line number Diff line number Diff line
@@ -93,7 +93,6 @@ struct sa_update_28xx {
};

#define        NUM_ENTRIES     256
#define        MAX_PAYLOAD     1024
#define        PUR_GET         1

struct dinfo {
@@ -127,6 +126,8 @@ struct enode {
	} u;
};

#define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))

#define EDIF_SESSION_DOWN(_s) \
	(qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
	 _s->disc_state == DSC_DELETED || \
+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@
#define __QLA_EDIF_BSG_H

/* BSG Vendor specific commands */
#define	ELS_MAX_PAYLOAD		1024
#define	ELS_MAX_PAYLOAD		2112
#ifndef	WWN_SIZE
#define WWN_SIZE		8
#endif
+4 −0
Original line number Diff line number Diff line
@@ -4486,6 +4486,10 @@ qla2x00_init_rings(scsi_qla_host_t *vha)
		    (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
	}

	/* ELS pass through payload is limit by frame size. */
	if (ha->flags.edif_enabled)
		mid_init_cb->init_cb.frame_payload_size = cpu_to_le16(ELS_MAX_PAYLOAD);

	rval = qla2x00_init_firmware(vha, ha->init_cb_size);
next_check:
	if (rval) {
+1 −1
Original line number Diff line number Diff line
@@ -4352,7 +4352,7 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,

	/* allocate the purex dma pool */
	ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
	    MAX_PAYLOAD, 8, 0);
	    ELS_MAX_PAYLOAD, 8, 0);

	if (!ha->purex_dma_pool) {
		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,