Loading drivers/gpu/drm/nouveau/include/nvkm/core/device.h +2 −2 Original line number Diff line number Diff line Loading @@ -171,7 +171,7 @@ struct nvkm_device { struct nvkm_engine *mspdec; struct nvkm_engine *msppp; struct nvkm_engine *msvld; struct nvkm_engine *nvenc[3]; struct nvkm_nvenc *nvenc[3]; struct nvkm_nvdec *nvdec[3]; struct nvkm_pm *pm; struct nvkm_engine *sec; Loading Loading @@ -245,7 +245,7 @@ struct nvkm_device_chip { int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_engine **); int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **); int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **); int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **); int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **); Loading drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h +10 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: MIT */ #ifndef __NVKM_NVENC_H__ #define __NVKM_NVENC_H__ #define nvkm_nvenc(p) container_of((p), struct nvkm_nvenc, engine) #include <core/engine.h> #include <core/falcon.h> struct nvkm_nvenc { const struct nvkm_nvenc_func *func; struct nvkm_engine engine; struct nvkm_falcon falcon; }; int gm107_nvenc_new(struct nvkm_device *, int, struct nvkm_nvenc **); #endif drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +27 −3 Original line number Diff line number Diff line Loading @@ -1988,6 +1988,7 @@ nv117_chipset = { .fifo = gm107_fifo_new, .gr = gm107_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2059,6 +2060,8 @@ nv120_chipset = { .fifo = gm200_fifo_new, .gr = gm200_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2096,6 +2099,8 @@ nv124_chipset = { .fifo = gm200_fifo_new, .gr = gm200_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2133,6 +2138,7 @@ nv126_chipset = { .fifo = gm200_fifo_new, .gr = gm200_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2197,6 +2203,9 @@ nv130_chipset = { .fifo = gp100_fifo_new, .gr = gp100_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .nvenc[2] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2233,6 +2242,8 @@ nv132_chipset = { .fifo = gp100_fifo_new, .gr = gp102_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2270,6 +2281,8 @@ nv134_chipset = { .fifo = gp100_fifo_new, .gr = gp104_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2307,6 +2320,7 @@ nv136_chipset = { .fifo = gp100_fifo_new, .gr = gp104_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2344,6 +2358,8 @@ nv137_chipset = { .fifo = gp100_fifo_new, .gr = gp107_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2449,6 +2465,9 @@ nv140_chipset = { .fifo = gv100_fifo_new, .gr = gv100_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .nvenc[2] = gm107_nvenc_new, .sec2 = gp108_sec2_new, }; Loading Loading @@ -2484,6 +2503,7 @@ nv162_chipset = { .dma = gv100_dma_new, .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2520,6 +2540,7 @@ nv164_chipset = { .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvdec[1] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2557,6 +2578,7 @@ nv166_chipset = { .nvdec[0] = gm107_nvdec_new, .nvdec[1] = gm107_nvdec_new, .nvdec[2] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2592,6 +2614,7 @@ nv167_chipset = { .dma = gv100_dma_new, .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2627,6 +2650,7 @@ nv168_chipset = { .dma = gv100_dma_new, .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2724,9 +2748,9 @@ nvkm_device_engine(struct nvkm_device *device, int index) _(MSPDEC , device->mspdec , device->mspdec); _(MSPPP , device->msppp , device->msppp); _(MSVLD , device->msvld , device->msvld); _(NVENC0 , device->nvenc[0], device->nvenc[0]); _(NVENC1 , device->nvenc[1], device->nvenc[1]); _(NVENC2 , device->nvenc[2], device->nvenc[2]); _(NVENC0 , device->nvenc[0], &device->nvenc[0]->engine); _(NVENC1 , device->nvenc[1], &device->nvenc[1]->engine); _(NVENC2 , device->nvenc[2], &device->nvenc[2]->engine); _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine); _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine); _(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine); Loading drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild +2 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: MIT #nvkm-y += nvkm/engine/nvenc/base.o nvkm-y += nvkm/engine/nvenc/base.o nvkm-y += nvkm/engine/nvenc/gm107.o drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c 0 → 100644 +63 −0 Original line number Diff line number Diff line /* * Copyright 2019 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "priv.h" #include "priv.h" #include <core/firmware.h> static void * nvkm_nvenc_dtor(struct nvkm_engine *engine) { struct nvkm_nvenc *nvenc = nvkm_nvenc(engine); nvkm_falcon_dtor(&nvenc->falcon); return nvenc; } static const struct nvkm_engine_func nvkm_nvenc = { .dtor = nvkm_nvenc_dtor, }; int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *fwif, struct nvkm_device *device, int index, struct nvkm_nvenc **pnvenc) { struct nvkm_nvenc *nvenc; int ret; if (!(nvenc = *pnvenc = kzalloc(sizeof(*nvenc), GFP_KERNEL))) return -ENOMEM; ret = nvkm_engine_ctor(&nvkm_nvenc, device, index, true, &nvenc->engine); if (ret) return ret; fwif = nvkm_firmware_load(&nvenc->engine.subdev, fwif, "Nvenc", nvenc); if (IS_ERR(fwif)) return -ENODEV; nvenc->func = fwif->func; return nvkm_falcon_ctor(nvenc->func->flcn, &nvenc->engine.subdev, nvkm_subdev_name[index], 0, &nvenc->falcon); }; Loading
drivers/gpu/drm/nouveau/include/nvkm/core/device.h +2 −2 Original line number Diff line number Diff line Loading @@ -171,7 +171,7 @@ struct nvkm_device { struct nvkm_engine *mspdec; struct nvkm_engine *msppp; struct nvkm_engine *msvld; struct nvkm_engine *nvenc[3]; struct nvkm_nvenc *nvenc[3]; struct nvkm_nvdec *nvdec[3]; struct nvkm_pm *pm; struct nvkm_engine *sec; Loading Loading @@ -245,7 +245,7 @@ struct nvkm_device_chip { int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_engine **); int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **); int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **); int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **); int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **); Loading
drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h +10 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: MIT */ #ifndef __NVKM_NVENC_H__ #define __NVKM_NVENC_H__ #define nvkm_nvenc(p) container_of((p), struct nvkm_nvenc, engine) #include <core/engine.h> #include <core/falcon.h> struct nvkm_nvenc { const struct nvkm_nvenc_func *func; struct nvkm_engine engine; struct nvkm_falcon falcon; }; int gm107_nvenc_new(struct nvkm_device *, int, struct nvkm_nvenc **); #endif
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +27 −3 Original line number Diff line number Diff line Loading @@ -1988,6 +1988,7 @@ nv117_chipset = { .fifo = gm107_fifo_new, .gr = gm107_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2059,6 +2060,8 @@ nv120_chipset = { .fifo = gm200_fifo_new, .gr = gm200_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2096,6 +2099,8 @@ nv124_chipset = { .fifo = gm200_fifo_new, .gr = gm200_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2133,6 +2138,7 @@ nv126_chipset = { .fifo = gm200_fifo_new, .gr = gm200_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2197,6 +2203,9 @@ nv130_chipset = { .fifo = gp100_fifo_new, .gr = gp100_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .nvenc[2] = gm107_nvenc_new, .sw = gf100_sw_new, }; Loading Loading @@ -2233,6 +2242,8 @@ nv132_chipset = { .fifo = gp100_fifo_new, .gr = gp102_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2270,6 +2281,8 @@ nv134_chipset = { .fifo = gp100_fifo_new, .gr = gp104_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2307,6 +2320,7 @@ nv136_chipset = { .fifo = gp100_fifo_new, .gr = gp104_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2344,6 +2358,8 @@ nv137_chipset = { .fifo = gp100_fifo_new, .gr = gp107_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .sec2 = gp102_sec2_new, .sw = gf100_sw_new, }; Loading Loading @@ -2449,6 +2465,9 @@ nv140_chipset = { .fifo = gv100_fifo_new, .gr = gv100_gr_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .nvenc[1] = gm107_nvenc_new, .nvenc[2] = gm107_nvenc_new, .sec2 = gp108_sec2_new, }; Loading Loading @@ -2484,6 +2503,7 @@ nv162_chipset = { .dma = gv100_dma_new, .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2520,6 +2540,7 @@ nv164_chipset = { .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvdec[1] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2557,6 +2578,7 @@ nv166_chipset = { .nvdec[0] = gm107_nvdec_new, .nvdec[1] = gm107_nvdec_new, .nvdec[2] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2592,6 +2614,7 @@ nv167_chipset = { .dma = gv100_dma_new, .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2627,6 +2650,7 @@ nv168_chipset = { .dma = gv100_dma_new, .fifo = tu102_fifo_new, .nvdec[0] = gm107_nvdec_new, .nvenc[0] = gm107_nvenc_new, .sec2 = tu102_sec2_new, }; Loading Loading @@ -2724,9 +2748,9 @@ nvkm_device_engine(struct nvkm_device *device, int index) _(MSPDEC , device->mspdec , device->mspdec); _(MSPPP , device->msppp , device->msppp); _(MSVLD , device->msvld , device->msvld); _(NVENC0 , device->nvenc[0], device->nvenc[0]); _(NVENC1 , device->nvenc[1], device->nvenc[1]); _(NVENC2 , device->nvenc[2], device->nvenc[2]); _(NVENC0 , device->nvenc[0], &device->nvenc[0]->engine); _(NVENC1 , device->nvenc[1], &device->nvenc[1]->engine); _(NVENC2 , device->nvenc[2], &device->nvenc[2]->engine); _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine); _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine); _(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine); Loading
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild +2 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: MIT #nvkm-y += nvkm/engine/nvenc/base.o nvkm-y += nvkm/engine/nvenc/base.o nvkm-y += nvkm/engine/nvenc/gm107.o
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c 0 → 100644 +63 −0 Original line number Diff line number Diff line /* * Copyright 2019 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "priv.h" #include "priv.h" #include <core/firmware.h> static void * nvkm_nvenc_dtor(struct nvkm_engine *engine) { struct nvkm_nvenc *nvenc = nvkm_nvenc(engine); nvkm_falcon_dtor(&nvenc->falcon); return nvenc; } static const struct nvkm_engine_func nvkm_nvenc = { .dtor = nvkm_nvenc_dtor, }; int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *fwif, struct nvkm_device *device, int index, struct nvkm_nvenc **pnvenc) { struct nvkm_nvenc *nvenc; int ret; if (!(nvenc = *pnvenc = kzalloc(sizeof(*nvenc), GFP_KERNEL))) return -ENOMEM; ret = nvkm_engine_ctor(&nvkm_nvenc, device, index, true, &nvenc->engine); if (ret) return ret; fwif = nvkm_firmware_load(&nvenc->engine.subdev, fwif, "Nvenc", nvenc); if (IS_ERR(fwif)) return -ENODEV; nvenc->func = fwif->func; return nvkm_falcon_ctor(nvenc->func->flcn, &nvenc->engine.subdev, nvkm_subdev_name[index], 0, &nvenc->falcon); };