Commit 13738a36 authored by Like Xu's avatar Like Xu Committed by Sean Christopherson
Browse files

perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models 



According to Intel SDM, the EPT-friendly PEBS is supported by all the
platforms after ICX, ADL and the future platforms with PEBS format 5.

Currently the only in-kernel user of this capability is KVM, which has
very limited support for hybrid core pmu, so ADL and its successors do
not currently expose this capability. When both hybrid core and PEBS
format 5 are present, KVM will decide on its own merits.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-perf-users@vger.kernel.org
Suggested-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarLike Xu <likexu@tencent.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221109082802.27543-4-likexu@tencent.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 974850be

arch/x86/events/intel/core.c

+1 −0
Original line number Diff line number Diff line
@@ -6348,6 +6348,7 @@ __init int intel_pmu_init(void) 
		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		x86_pmu.limit_period = spr_limit_period;

		x86_pmu.pebs_ept = 1;

		x86_pmu.pebs_aliases = NULL;

		x86_pmu.pebs_prec_dist = true;

		x86_pmu.pebs_block = true;

arch/x86/events/intel/ds.c

+3 −1
Original line number Diff line number Diff line
@@ -2303,8 +2303,10 @@ void __init intel_ds_init(void) 
			x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;

			break;



		case 4:

		case 5:

			x86_pmu.pebs_ept = 1;

			fallthrough;

		case 4:

			x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;

			x86_pmu.pebs_record_size = sizeof(struct pebs_basic);

			if (x86_pmu.intel_cap.pebs_baseline) {