Unverified Commit 13a45b94 authored by YC Hung's avatar YC Hung Committed by Mark Brown
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ASoC: SOF: mediatek: Revise mt8195 boot flow 



1. Revise hifixdsp shutdown flow to pull runstall high then reset high.
2. Add 1 us delay between D/BRESET high and low for 10 DSP cycles(26M)
   based on IP vendor's suggestion.

Signed-off-by: default avatarYC Hung <yc.hung@mediatek.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarLi-Yu Yu <afg984@gmail.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarKuanHsun Cheng <Allen-KH.Cheng@mediatek.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220708203904.29214-2-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7d596d9b

sound/soc/sof/mediatek/mt8195/mt8195-loader.c

+8 −3
Original line number Diff line number Diff line
@@ -29,6 +29,9 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) 
				ADSP_BRESET_SW | ADSP_DRESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW);



	/* delay 10 DSP cycles at 26M about 1us by IP vendor's suggestion */

	udelay(1);



	/* pull low DReset & BReset */

	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW,
@@ -46,11 +49,13 @@ void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) 


void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)

{

	/* Clear to 0 firstly */

	snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_RESET_SW, 0x0);



	/* RUN_STALL pull high again to reset */

	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,

				ADSP_RUNSTALL, ADSP_RUNSTALL);



	/* pull high DReset & BReset */

	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW,

				ADSP_BRESET_SW | ADSP_DRESET_SW);

}