Commit 158858bf authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: rework macros for DWB register access 



[Why]
A hack was used to access DWB register due to difference in the register
naming convention which was not compatible with existing SR/SRI* macros.
The additional macro needed were added to dwb ip specific header file
(dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to
this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in
turn needed us to undefine them in the resource file.

[How]
Add a separate macro for DWB access to the resource files that need it
instead of defining them in DWB ip header file. This will enable us to
reuse the BASE macro defined in the resource file.

Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bcdc9158

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

+168 −195
Original line number Diff line number Diff line
@@ -27,204 +27,177 @@ 
#define TO_DCN20_DWBC(dwbc_base) \

	container_of(dwbc_base, struct dcn20_dwbc, base)



/* DCN */

#define BASE_INNER(seg) \

	DCE_BASE__INST0_SEG ## seg



#define BASE(seg) \

	BASE_INNER(seg)



#define SR(reg_name)\

		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \

					mm ## reg_name



#define SRI(reg_name, block, id)\

	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name



#define SRI2(reg_name, block, id)\

	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

					mm ## reg_name



#define SRII(reg_name, block, id)\

	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name



#define SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix





#define DWBC_COMMON_REG_LIST_DCN2_0(inst) \

	SRI2(WB_ENABLE, CNV, inst),\

	SRI2(WB_EC_CONFIG, CNV, inst),\

	SRI2(CNV_MODE, CNV, inst),\

	SRI2(CNV_WINDOW_START, CNV, inst),\

	SRI2(CNV_WINDOW_SIZE, CNV, inst),\

	SRI2(CNV_UPDATE, CNV, inst),\

	SRI2(CNV_SOURCE_SIZE, CNV, inst),\

	SRI2(CNV_TEST_CNTL, CNV, inst),\

	SRI2(CNV_TEST_CRC_RED, CNV, inst),\

	SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\

	SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\

	SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\

	SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\

	SRI2(WBSCL_MODE, WBSCL, inst),\

	SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\

	SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\

	SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\

	SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\

	SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\

	SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\

	SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\

	SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\

	SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\

	SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\

	SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\

	SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\

	SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\

	SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\

	SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\

	SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\

	SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\

	SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\

	SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\

	SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\

	SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\

	SRI2(WBSCL_DEBUG, WBSCL, inst),\

	SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\

	SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\

	SRI2(WB_DEBUG_CTRL, CNV, inst),\

	SRI2(WB_DBG_MODE, CNV, inst),\

	SRI2(WB_HW_DEBUG, CNV, inst),\

	SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\

	SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\

	SRI2(WB_SOFT_RESET, CNV, inst),\

	SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\

	SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst)

	SRI2_DWB(WB_ENABLE, CNV, inst),\

	SRI2_DWB(WB_EC_CONFIG, CNV, inst),\

	SRI2_DWB(CNV_MODE, CNV, inst),\

	SRI2_DWB(CNV_WINDOW_START, CNV, inst),\

	SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\

	SRI2_DWB(CNV_UPDATE, CNV, inst),\

	SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\

	SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\

	SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\

	SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\

	SRI2_DWB(CNV_TEST_CRC_BLUE, CNV, inst),\

	SRI2_DWB(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\

	SRI2_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\

	SRI2_DWB(WBSCL_MODE, WBSCL, inst),\

	SRI2_DWB(WBSCL_TAP_CONTROL, WBSCL, inst),\

	SRI2_DWB(WBSCL_DEST_SIZE, WBSCL, inst),\

	SRI2_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\

	SRI2_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\

	SRI2_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\

	SRI2_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\

	SRI2_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\

	SRI2_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\

	SRI2_DWB(WBSCL_ROUND_OFFSET, WBSCL, inst),\

	SRI2_DWB(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\

	SRI2_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\

	SRI2_DWB(WBSCL_TEST_CNTL, WBSCL, inst),\

	SRI2_DWB(WBSCL_TEST_CRC_RED, WBSCL, inst),\

	SRI2_DWB(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\

	SRI2_DWB(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\

	SRI2_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\

	SRI2_DWB(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\

	SRI2_DWB(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\

	SRI2_DWB(WBSCL_CLAMP_CBCR, WBSCL, inst),\

	SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\

	SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\

	SRI2_DWB(WBSCL_DEBUG, WBSCL, inst),\

	SRI2_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\

	SRI2_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\

	SRI2_DWB(WB_DEBUG_CTRL, CNV, inst),\

	SRI2_DWB(WB_DBG_MODE, CNV, inst),\

	SRI2_DWB(WB_HW_DEBUG, CNV, inst),\

	SRI2_DWB(CNV_TEST_DEBUG_INDEX, CNV, inst),\

	SRI2_DWB(CNV_TEST_DEBUG_DATA, CNV, inst),\

	SRI2_DWB(WB_SOFT_RESET, CNV, inst),\

	SRI2_DWB(WB_WARM_UP_MODE_CTL1, CNV, inst),\

	SRI2_DWB(WB_WARM_UP_MODE_CTL2, CNV, inst)



#define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \

	SF(WB_ENABLE, WB_ENABLE, mask_sh),\

	SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\

	SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\

	SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\

	SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\

	SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\

	SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\

	SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\

	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\

	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\

	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\

	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\

	SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\

	SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\

	SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\

	SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\

	SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\

	SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\

	SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\

	SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\

	SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\

	SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\

	SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\

	SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\

	SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\

	SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\

	SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\

	SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\

	SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\

	SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\

	SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\

	SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\

	SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\

	SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\

	SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\

	SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\

	SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\

	SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\

	SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\

	SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\

	SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\

	SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\

	SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\

	SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\

	SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\

	SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\

	SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\

	SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\

	SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\

	SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\

	SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\

	SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\

	SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\

	SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\

	SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\

	SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\

	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\

	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\

	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\

	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\

	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\

	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\

	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\

	SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\

	SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\

	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\

	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\

	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\

	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\

	SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\

	SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\

	SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\

	SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\

	SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\

	SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\

	SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\

	SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\

	SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\

	SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\

	SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\

	SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\

	SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\

	SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\

	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\

	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\

	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\

	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\

	SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\

	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\

	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\

	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\

	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\

	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\

	SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\

	SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\

	SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\

	SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\

	SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\

	SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\

	SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\

	SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\

	SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\

	SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\

	SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\

	SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\

	SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\

	SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\

	SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\

	SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\

	SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\

	SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\

	SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\

	SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\

	SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\

	SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\

	SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\

	SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\

	SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\

	SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\

	SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\

	SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\

	SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)

	SF_DWB(WB_ENABLE, WB_ENABLE, mask_sh),\

	SF_DWB(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\

	SF_DWB(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\

	SF_DWB(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\

	SF_DWB(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\

	SF_DWB(CNV_MODE, CNV_OUT_BPC, mask_sh),\

	SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\

	SF_DWB(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\

	SF_DWB(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\

	SF_DWB(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\

	SF_DWB(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\

	SF_DWB(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\

	SF_DWB(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\

	SF_DWB(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\

	SF_DWB(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\

	SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\

	SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\

	SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\

	SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\

	SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\

	SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\

	SF_DWB(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\

	SF_DWB(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\

	SF_DWB(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\

	SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\

	SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\

	SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\

	SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\

	SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\

	SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\

	SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\

	SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\

	SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\

	SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\

	SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\

	SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\

	SF_DWB(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\

	SF_DWB(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\

	SF_DWB(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\

	SF_DWB(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\

	SF_DWB(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\

	SF_DWB(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\

	SF_DWB(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\

	SF_DWB(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\

	SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\

	SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\

	SF_DWB(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\

	SF_DWB(WBSCL_MODE, WBSCL_MODE, mask_sh),\

	SF_DWB(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\

	SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\

	SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\

	SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\

	SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\

	SF_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\

	SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\

	SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\

	SF_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\

	SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\

	SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\

	SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\

	SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\

	SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\

	SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\

	SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\

	SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\

	SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\

	SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\

	SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\

	SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\

	SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\

	SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\

	SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\

	SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\

	SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\

	SF_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\

	SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\

	SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\

	SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\

	SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\

	SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\

	SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\

	SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\

	SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\

	SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\

	SF_DWB(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\

	SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\

	SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\

	SF_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\

	SF_DWB(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\

	SF_DWB(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\

	SF_DWB(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\

	SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\

	SF_DWB(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\

	SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)



#define DWBC_REG_FIELD_LIST_DCN2_0(type) \

	type WB_ENABLE;\

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h

+0 −7
Original line number Diff line number Diff line
@@ -29,13 +29,6 @@ 
#define TO_DCN20_MMHUBBUB(mcif_wb_base) \

	container_of(mcif_wb_base, struct dcn20_mmhubbub, base)



/* DCN */

#define BASE_INNER(seg) \

	DCE_BASE__INST0_SEG ## seg



#define BASE(seg) \

	BASE_INNER(seg)



#define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \

	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\

	SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+9 −2
Original line number Diff line number Diff line
@@ -124,8 +124,6 @@ enum dcn20_clk_src_array_id { 
 * macros to expend register list macro defined in HW object header file */



/* DCN */

/* TODO awful hack. fixup dcn20_dwb.h */

#undef BASE_INNER

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg



#define BASE(seg) BASE_INNER(seg)
@@ -138,6 +136,15 @@ enum dcn20_clk_src_array_id { 
	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name



#define SRI2_DWB(reg_name, block, id)\

	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

					mm ## reg_name

#define SF_DWB(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix



#define SF_DWB2(reg_name, block, id, field_name, post_fix)	\

	.field_name = reg_name ## __ ## field_name ## post_fix



#define SRIR(var_name, reg_name, block, id)\

	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					mm ## block ## id ## _ ## reg_name

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h

+0 −6
Original line number Diff line number Diff line
@@ -28,12 +28,6 @@ 


#include "vmid.h"



#define BASE_INNER(seg) \

	DCE_BASE__INST0_SEG ## seg



#define BASE(seg) \

	BASE_INNER(seg)



#define DCN20_VMID_REG_LIST(id)\

	SRI(CNTL, DCN_VM_CONTEXT, id),\

	SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+0 −2
Original line number Diff line number Diff line
@@ -94,8 +94,6 @@ 
 * macros to expend register list macro defined in HW object header file */



/* DCN */

/* TODO awful hack. fixup dcn20_dwb.h */

#undef BASE_INNER

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg



#define BASE(seg) BASE_INNER(seg)