Commit 15ca3549 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools arch x86: Sync the msr-index.h copy with the kernel sources 

To pick up the changes from these csets:

  1b5277c0 ("x86/srso: Add SRSO_NO support")
  8974eb58 ("x86/speculation: Add Gather Data Sampling mitigation")

That cause no changes to tooling:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
  $ diff -u before after
  $

Just silences this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov (AMD) <bp@alien8.de>
Cc: Daniel Sneddon <daniel.sneddon@linux.intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/lkml/ZQGismCqcDddjEIQ@kernel.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 678ddf73

tools/arch/x86/include/asm/msr-index.h

+12 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 


#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */

#define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */

#define PRED_CMD_SBPB			BIT(7)	   /* Selective Branch Prediction Barrier */



#define MSR_PPIN_CTL			0x0000004e

#define MSR_PPIN			0x0000004f
@@ -155,6 +156,15 @@ 
						 * Not susceptible to Post-Barrier

						 * Return Stack Buffer Predictions.

						 */

#define ARCH_CAP_GDS_CTRL		BIT(25)	/*

						 * CPU is vulnerable to Gather

						 * Data Sampling (GDS) and

						 * has controls for mitigation.

						 */

#define ARCH_CAP_GDS_NO			BIT(26)	/*

						 * CPU is not vulnerable to Gather

						 * Data Sampling (GDS).

						 */



#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*

						 * IA32_XAPIC_DISABLE_STATUS MSR
@@ -178,6 +188,8 @@ 
#define RNGDS_MITG_DIS			BIT(0)	/* SRBDS support */

#define RTM_ALLOW			BIT(1)	/* TSX development mode */

#define FB_CLEAR_DIS			BIT(3)	/* CPU Fill buffer clear disable */

#define GDS_MITG_DIS			BIT(4)	/* Disable GDS mitigation */

#define GDS_MITG_LOCKED			BIT(5)	/* GDS mitigation locked */



#define MSR_IA32_SYSENTER_CS		0x00000174

#define MSR_IA32_SYSENTER_ESP		0x00000175