Commit 164f5900 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'microblaze-v6.2' of git://git.monstr.eu/linux-2.6-microblaze 

Pull microblaze updates from Michal Simek:
 "Clean up PCI support which was pretty much copied and pasted from
  PowerPC long time ago for one custom platform which is not available
  for years.

  Also, the Xilinx/AMD PCIe team tested Microblaze with IP cores also
  used on ARM SOCs and clean up Microblaze code"

* tag 'microblaze-v6.2' of git://git.monstr.eu/linux-2.6-microblaze:
  microblaze/PCI: Moving PCI iounmap and dependent code
  microblaze/PCI: Remove support for Xilinx PCI host bridge
  microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
  microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al declaration
  microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU address to I/O port
  microblaze/PCI: Remove unused PCI Indirect ops
  microblaze/PCI: Remove unused PCI BIOS resource allocation
  microblaze/PCI: Remove unused allocation & free of PCI host bridge structure
  microblaze/PCI: Remove unused device tree parsing for a host bridge resources
  microblaze/PCI: Remove unused PCI legacy IO's access on a bus
  microblaze/PCI: Remove unused PCI bus scan if configured as a host
  microblaze/PCI: Remove Null PCI config access unused functions
  microblaze/PCI: Remove unused early_read_config_byte() et al declarations
parents 7d621599 5cfe469c

arch/microblaze/Kconfig

+0 −8
Original line number Diff line number Diff line
@@ -215,11 +215,3 @@ config MB_MANAGER 
	  Say N here unless you know what you are doing.



endmenu
 


menu "Bus Options"



config PCI_XILINX

	bool "Xilinx PCI host bridge support"

	depends on PCI



endmenu

arch/microblaze/configs/mmu_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -19,7 +19,6 @@ CONFIG_HZ_100=y 
CONFIG_CMDLINE_BOOL=y

CONFIG_CMDLINE_FORCE=y

CONFIG_HIGHMEM=y

CONFIG_PCI_XILINX=y

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

# CONFIG_BLK_DEV_BSG is not set

arch/microblaze/include/asm/pci-bridge.h

+0 −92
Original line number Diff line number Diff line
@@ -25,75 +25,17 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address) 
 */

struct pci_controller {

	struct pci_bus *bus;

	char is_dynamic;

	struct device_node *dn;

	struct list_head list_node;

	struct device *parent;



	int first_busno;

	int last_busno;



	int self_busno;



	void __iomem *io_base_virt;

	resource_size_t io_base_phys;



	resource_size_t pci_io_size;



	/* Some machines (PReP) have a non 1:1 mapping of

	 * the PCI memory space in the CPU bus space

	 */

	resource_size_t pci_mem_offset;



	/* Some machines have a special region to forward the ISA

	 * "memory" cycles such as VGA memory regions. Left to 0

	 * if unsupported

	 */

	resource_size_t isa_mem_phys;

	resource_size_t isa_mem_size;



	struct pci_ops *ops;

	unsigned int __iomem *cfg_addr;

	void __iomem *cfg_data;



	/*

	 * Used for variants of PCI indirect handling and possible quirks:

	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1

	 *  EXT_REG - provides access to PCI-e extended registers

	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS

	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS

	 *   to determine which bus number to match on when generating type0

	 *   config cycles

	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with

	 *   hanging if we don't have link and try to do config cycles to

	 *   anything but the PHB.  Only allow talking to the PHB if this is

	 *   set.

	 *  BIG_ENDIAN - cfg_addr is a big endian register

	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs

	 *   on the PLB4.  Effectively disable MRM commands by setting this.

	 */

#define INDIRECT_TYPE_SET_CFG_TYPE		0x00000001

#define INDIRECT_TYPE_EXT_REG		0x00000002

#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004

#define INDIRECT_TYPE_NO_PCIE_LINK		0x00000008

#define INDIRECT_TYPE_BIG_ENDIAN		0x00000010

#define INDIRECT_TYPE_BROKEN_MRM		0x00000020

	u32 indirect_type;



	/* Currently, we limit ourselves to 1 IO range and 3 mem

	 * ranges since the common pci_bus structure can't handle more

	 */

	struct resource io_resource;

	struct resource mem_resources[3];

	int global_number;	/* PCI domain number */

};



#ifdef CONFIG_PCI

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)

{

	return bus->sysdata;

}



static inline int isa_vaddr_is_ioport(void __iomem *address)

{

	/* No specific ISA handling on ppc32 at this stage, it
@@ -103,39 +45,5 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) 
}

#endif /* CONFIG_PCI */



/* These are used for config access before all the PCI probing

   has been done. */

extern int early_read_config_byte(struct pci_controller *hose, int bus,

			int dev_fn, int where, u8 *val);

extern int early_read_config_word(struct pci_controller *hose, int bus,

			int dev_fn, int where, u16 *val);

extern int early_read_config_dword(struct pci_controller *hose, int bus,

			int dev_fn, int where, u32 *val);

extern int early_write_config_byte(struct pci_controller *hose, int bus,

			int dev_fn, int where, u8 val);

extern int early_write_config_word(struct pci_controller *hose, int bus,

			int dev_fn, int where, u16 val);

extern int early_write_config_dword(struct pci_controller *hose, int bus,

			int dev_fn, int where, u32 val);



extern int early_find_capability(struct pci_controller *hose, int bus,

				 int dev_fn, int cap);



extern void setup_indirect_pci(struct pci_controller *hose,

			       resource_size_t cfg_addr,

			       resource_size_t cfg_data, u32 flags);



/* Get the PCI host controller for an OF device */

extern struct pci_controller *pci_find_hose_for_OF_device(

			struct device_node *node);



/* Fill up host controller resources from the OF node */

extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,

			struct device_node *dev, int primary);



/* Allocate & free a PCI host bridge structure */

extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);

extern void pcibios_free_controller(struct pci_controller *phb);



#endif	/* __KERNEL__ */

#endif	/* _ASM_MICROBLAZE_PCI_BRIDGE_H */

arch/microblaze/include/asm/pci.h

+0 −29
Original line number Diff line number Diff line
@@ -21,15 +21,6 @@ 
#define PCIBIOS_MIN_IO		0x1000

#define PCIBIOS_MIN_MEM		0x10000000



/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */

#define IOBASE_BRIDGE_NUMBER	0

#define IOBASE_MEMORY		1

#define IOBASE_IO		2

#define IOBASE_ISA_IO		3

#define IOBASE_ISA_MEM		4



#define pcibios_scan_all_fns(a, b)	0



/*

 * Set this to 1 if you want the kernel to re-assign all PCI

 * bus numbers (don't do that on ppc64 yet !)
@@ -41,33 +32,13 @@ extern int pci_domain_nr(struct pci_bus *bus); 
/* Decide whether to display the domain number in /proc */

extern int pci_proc_domain(struct pci_bus *bus);



struct vm_area_struct;



/* Tell PCI code what kind of PCI resource mappings we support */

#define HAVE_PCI_MMAP			1

#define ARCH_GENERIC_PCI_MMAP_RESOURCE	1

#define arch_can_pci_mmap_io()		1



extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,

			   size_t count);

extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,

			   size_t count);

extern int pci_mmap_legacy_page_range(struct pci_bus *bus,

				      struct vm_area_struct *vma,

				      enum pci_mmap_state mmap_state);



#define HAVE_PCI_LEGACY	1



extern void pcibios_resource_survey(void);



struct file;



/* This part of code was originally in xilinx-pci.h */

#ifdef CONFIG_PCI_XILINX

extern void __init xilinx_pci_init(void);

#else

static inline void __init xilinx_pci_init(void) { return; }

#endif



#endif	/* __KERNEL__ */

#endif /* __ASM_MICROBLAZE_PCI_H */

arch/microblaze/pci/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -3,5 +3,4 @@ 
# Makefile

#



obj-$(CONFIG_PCI)		+= pci-common.o indirect_pci.o iomap.o

obj-$(CONFIG_PCI_XILINX)	+= xilinx_pci.o
 
obj-$(CONFIG_PCI)		+= iomap.o