Commit 170285f4 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fields 



Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 183 bytes.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e50f9c8ef1261b7ceb6b1be637d4019fe7312250.1649865241.git.geert+renesas@glider.be
parent b9f01b20

drivers/pinctrl/renesas/pfc-r8a779f0.c

+27 −60
Original line number Diff line number Diff line
@@ -144,9 +144,6 @@ 
#define IP2SR0_11_8	FM(IRQ1)		F_(0, 0)		F_(0, 0)		FM(MSIOF1_SS2)		F_(0, 0)	FM(TSN0_PHY_INT_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR0_15_12	FM(IRQ2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(TSN1_PHY_INT_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR0_19_16	FM(IRQ3)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(TSN2_PHY_INT_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR0_23_20	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR0_27_24	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR0_31_28	F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* IP0SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */		/* 5 */			/* 6 */			/* 7 - F */

#define IP0SR1_3_0	FM(GP1_00)		FM(TCLK1)		FM(HSCK2)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -192,9 +189,9 @@ FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 
FM(IP0SR0_11_8)		IP0SR0_11_8	FM(IP1SR0_11_8)		IP1SR0_11_8	FM(IP2SR0_11_8)		IP2SR0_11_8	\

FM(IP0SR0_15_12)	IP0SR0_15_12	FM(IP1SR0_15_12)	IP1SR0_15_12	FM(IP2SR0_15_12)	IP2SR0_15_12	\

FM(IP0SR0_19_16)	IP0SR0_19_16	FM(IP1SR0_19_16)	IP1SR0_19_16	FM(IP2SR0_19_16)	IP2SR0_19_16	\

FM(IP0SR0_23_20)	IP0SR0_23_20	FM(IP1SR0_23_20)	IP1SR0_23_20	FM(IP2SR0_23_20)	IP2SR0_23_20	\

FM(IP0SR0_27_24)	IP0SR0_27_24	FM(IP1SR0_27_24)	IP1SR0_27_24	FM(IP2SR0_27_24)	IP2SR0_27_24	\

FM(IP0SR0_31_28)	IP0SR0_31_28	FM(IP1SR0_31_28)	IP1SR0_31_28	FM(IP2SR0_31_28)	IP2SR0_31_28	\

FM(IP0SR0_23_20)	IP0SR0_23_20	FM(IP1SR0_23_20)	IP1SR0_23_20	\

FM(IP0SR0_27_24)	IP0SR0_27_24	FM(IP1SR0_27_24)	IP1SR0_27_24	\

FM(IP0SR0_31_28)	IP0SR0_31_28	FM(IP1SR0_31_28)	IP1SR0_31_28	\

\

FM(IP0SR1_3_0)		IP0SR1_3_0	\

FM(IP0SR1_7_4)		IP0SR1_7_4	\
@@ -1620,18 +1617,11 @@ static const struct sh_pfc_function pinmux_functions[] = { 
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

#define F_(x, y)	FN_##y

#define FM(x)		FN_##x

	{ PINMUX_CFG_REG("GPSR0", 0xe6050040, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,

			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP0_31_21 RESERVED */

		GP_0_20_FN,	GPSR0_20,

		GP_0_19_FN,	GPSR0_19,

		GP_0_18_FN,	GPSR0_18,
@@ -1654,14 +1644,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_0_1_FN,	GPSR0_1,

		GP_0_0_FN,	GPSR0_0, ))

	},

	{ PINMUX_CFG_REG("GPSR1", 0xe6050840, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,

			     GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP1_31_25 RESERVED */

		GP_1_24_FN,	GPSR1_24,

		GP_1_23_FN,	GPSR1_23,

		GP_1_22_FN,	GPSR1_22,
@@ -1688,22 +1675,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_1_1_FN,	GPSR1_1,

		GP_1_0_FN,	GPSR1_0, ))

	},

	{ PINMUX_CFG_REG("GPSR2", 0xe6051040, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,

			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP2_31_17 RESERVED */

		GP_2_16_FN,	GPSR2_16,

		GP_2_15_FN,	GPSR2_15,

		GP_2_14_FN,	GPSR2_14,
@@ -1722,20 +1698,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_2_1_FN,	GPSR2_1,

		GP_2_0_FN,	GPSR2_0, ))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xe6051840, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,

			     GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP3_31_19 RESERVED */

		GP_3_18_FN,	GPSR3_18,

		GP_3_17_FN,	GPSR3_17,

		GP_3_16_FN,	GPSR3_16,
@@ -1781,10 +1748,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		IP1SR0_7_4

		IP1SR0_3_0))

	},

	{ PINMUX_CFG_REG("IP2SR0", 0xe6050068, 32, 4, GROUP(

		IP2SR0_31_28

		IP2SR0_27_24

		IP2SR0_23_20

	{ PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,

			     GROUP(-12, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP2SR0_31_20 RESERVED */

		IP2SR0_19_16

		IP2SR0_15_12

		IP2SR0_11_8