Commit 18a20784 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v6.2-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull clockevent/source driver updates from Daniel Lezcano:

  - Add DT bindings for the Rockchip rk3128 timer (Johan Jonker)

  - Change the DT bindings for the npcm7xx timer in order to specify
    multiple clocks and enable the clock for the timer1 on WPCM450
    (Jonathan Neuschäfer)

  - Fix the timer duration being too long the ARM architected timer in
    order to prevent an integer overflow leading to a negative value and
    an immediate interruption (Joe Korty)

  - Fix an unused pointer warning reported by lkp and some cleanups in
    the timer TI dm (Tony Lindgren)

  - Fix a missing call to clk_disable_unprepare() in the error path at
    init time on the timer TI dm (Yang Yingliang)

  - Use kstrtobool() instead of strtobool() in the ARM architected timer
    (Christophe JAILLET)

  - Add DT bindings for r8a779g0 on Renesas platform (Wolfram Sang)

Link: https://lore.kernel.org/all/3c4c3bb2-b849-0c87-0948-8a36984bdde4@linaro.org
parents ebe11732 83571a43

Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml

+7 −1
Original line number Diff line number Diff line
@@ -25,7 +25,13 @@ properties: 
      - description: The timer interrupt of timer 0



  clocks:

    maxItems: 1

    items:

      - description: The reference clock for timer 0

      - description: The reference clock for timer 1

      - description: The reference clock for timer 2

      - description: The reference clock for timer 3

      - description: The reference clock for timer 4

    minItems: 1



required:

  - compatible

Documentation/devicetree/bindings/timer/renesas,cmt.yaml

+2 −0
Original line number Diff line number Diff line
@@ -102,12 +102,14 @@ properties: 
          - enum:

              - renesas,r8a779a0-cmt0     # 32-bit CMT0 on R-Car V3U

              - renesas,r8a779f0-cmt0     # 32-bit CMT0 on R-Car S4-8

              - renesas,r8a779g0-cmt0     # 32-bit CMT0 on R-Car V4H

          - const: renesas,rcar-gen4-cmt0 # 32-bit CMT0 on R-Car Gen4



      - items:

          - enum:

              - renesas,r8a779a0-cmt1     # 48-bit CMT on R-Car V3U

              - renesas,r8a779f0-cmt1     # 48-bit CMT on R-Car S4-8

              - renesas,r8a779g0-cmt1     # 48-bit CMT on R-Car V4H

          - const: renesas,rcar-gen4-cmt1 # 48-bit CMT on R-Car Gen4



  reg:

Documentation/devicetree/bindings/timer/renesas,tmu.yaml

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ properties: 
          - renesas,tmu-r8a77995 # R-Car D3

          - renesas,tmu-r8a779a0 # R-Car V3U

          - renesas,tmu-r8a779f0 # R-Car S4-8

          - renesas,tmu-r8a779g0 # R-Car V4H

      - const: renesas,tmu



  reg:

Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties: 
          - enum:

              - rockchip,rv1108-timer

              - rockchip,rk3036-timer

              - rockchip,rk3128-timer

              - rockchip,rk3188-timer

              - rockchip,rk3228-timer

              - rockchip,rk3229-timer

drivers/clocksource/arm_arch_timer.c

+7 −3
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <linux/clocksource.h>

#include <linux/clocksource_ids.h>

#include <linux/interrupt.h>

#include <linux/kstrtox.h>

#include <linux/of_irq.h>

#include <linux/of_address.h>

#include <linux/io.h>
@@ -97,7 +98,7 @@ static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EV 


static int __init early_evtstrm_cfg(char *buf)

{

	return strtobool(buf, &evtstrm_enable);

	return kstrtobool(buf, &evtstrm_enable);

}

early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
@@ -806,6 +807,9 @@ static u64 __arch_timer_check_delta(void) 
		/*

		 * XGene-1 implements CVAL in terms of TVAL, meaning

		 * that the maximum timer range is 32bit. Shame on them.

		 *

		 * Note that TVAL is signed, thus has only 31 of its

		 * 32 bits to express magnitude.

		 */

		MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,

						 APM_CPU_PART_POTENZA)),
@@ -813,8 +817,8 @@ static u64 __arch_timer_check_delta(void) 
	};



	if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {

		pr_warn_once("Broken CNTx_CVAL_EL1, limiting width to 32bits");

		return CLOCKSOURCE_MASK(32);

		pr_warn_once("Broken CNTx_CVAL_EL1, using 32 bit TVAL instead.\n");

		return CLOCKSOURCE_MASK(31);

	}

#endif

	return CLOCKSOURCE_MASK(arch_counter_get_width());