Commit 1937f3fe authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Tvrtko Ursulin
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drm/i915: Treat SAGV block time 0 as SAGV disabled 



For modern platforms the spec explicitly states that a
SAGV block time of zero means that SAGV is not supported.
Let's extend that to all platforms. Supposedly there should
be no systems where this isn't true, and it'll allow us to:
- use the same code regardless of older vs. newer platform
- wm latencies already treat 0 as disabled, so this fits well
  with other related code
- make it a bit more clear when SAGV is used vs. not
- avoid overflows from adding U32_MAX with a u16 wm0 latency value
  which could cause us to miscalculate the SAGV watermarks on tgl+

Cc: stable@vger.kernel.org
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309164948.10671-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
(cherry picked from commit d8f5855b)
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent 9cddf03b

drivers/gpu/drm/i915/intel_pm.c

+6 −4
Original line number Diff line number Diff line
@@ -3698,8 +3698,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv) 
		MISSING_CASE(DISPLAY_VER(dev_priv));

	}



	/* Default to an unusable block time */

	dev_priv->sagv_block_time_us = -1;

	dev_priv->sagv_block_time_us = 0;

}



/*
@@ -5645,7 +5644,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 
	result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;

	result->enable = true;



	if (DISPLAY_VER(dev_priv) < 12)

	if (DISPLAY_VER(dev_priv) < 12 && dev_priv->sagv_block_time_us)

		result->can_sagv = latency >= dev_priv->sagv_block_time_us;

}
@@ -5678,7 +5677,10 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, 
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;

	struct skl_wm_level *levels = plane_wm->wm;

	unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;

	unsigned int latency = 0;



	if (dev_priv->sagv_block_time_us)

		latency = dev_priv->sagv_block_time_us + dev_priv->wm.skl_latency[0];



	skl_compute_plane_wm(crtc_state, plane, 0, latency,

			     wm_params, &levels[0],