Commit 19d9a846 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Jakub Kicinski
Browse files

dt-binding: net: ti: k3-am654-cpsw-nuss: update bindings for am64x cpsw3g 

Update DT binding for recently introduced TI K3 AM642x SoC [1] which
contains 3 port (2 external ports) CPSW3g module. The CPSW3g integrated
in MAIN domain and can be configured in multi port or switch modes.

The overall functionality and DT bindings are similar to other K3 CPSWxg
versions, so DT binding changes are minimal:
 - reword description
 - add new compatible 'ti,am642-cpsw-nuss'
 - allow 2 external ports child nodes
 - add missed 'assigned-clock' props

[1] https://www.ti.com/lit/pdf/spruim2


Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent b3228c74

Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

+30 −20
Original line number Original line Diff line number Diff line
@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#

$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#





title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings

title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings





maintainers:

maintainers:

  - Grygorii Strashko <grygorii.strashko@ti.com>

  - Grygorii Strashko <grygorii.strashko@ti.com>
@@ -13,19 +13,16 @@ maintainers: 
description:

description:

  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports

  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports

  (one external) and provides Ethernet packet communication for the device.

  (one external) and provides Ethernet packet communication for the device.

  CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),

  The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports

  Reduced Media Independent Interface (RMII), the Management Data

  (two external) and provides Ethernet packet communication and switching.

  Input/Output (MDIO) interface for physical layer device (PHY) management,



  new version of Common Platform Time Sync (CPTS), updated Address Lookup

  The internal Communications Port Programming Interface (CPPI5) (Host port 0).

  Engine (ALE).

  One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and

  an internal Communications Port Programming Interface (CPPI5) (Host port 0).

  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels

  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels

  and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA

  and one RX channels and operating by NAVSS Unified DMA  Peripheral Root

  Peripheral Root Complex (UDMA-P) controller.

  Complex (UDMA-P) controller.

  The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0.





  Additional features

  CPSWxG features

  updated Address Lookup Engine (ALE).

  priority level Quality Of Service (QOS) support (802.1p)

  priority level Quality Of Service (QOS) support (802.1p)

  Support for Audio/Video Bridging (P802.1Qav/D6.0)

  Support for Audio/Video Bridging (P802.1Qav/D6.0)

  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)

  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
@@ -38,10 +35,18 @@ description: 
  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on

  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on

  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.

  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.

  RX/TX csum offload

  RX/TX csum offload

  Management Data Input/Output (MDIO) interface for PHYs management

  RMII/RGMII Interfaces support

  new version of Common Platform Time Sync (CPTS)



  The CPSWxG NUSS is integrated into

    device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.

    device MAIN domain named CPSW0 on AM642x SoC.





  Specifications can be found at

  Specifications can be found at

    http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf

    https://www.ti.com/lit/pdf/spruid7

    http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf

    https://www.ti.com/lit/zip/spruil1

    https://www.ti.com/lit/pdf/spruim2





properties:

properties:

  "#address-cells": true

  "#address-cells": true
@@ -51,11 +56,12 @@ properties: 
    oneOf:

    oneOf:

      - const: ti,am654-cpsw-nuss

      - const: ti,am654-cpsw-nuss

      - const: ti,j721e-cpsw-nuss

      - const: ti,j721e-cpsw-nuss

      - const: ti,am642-cpsw-nuss





  reg:

  reg:

    maxItems: 1

    maxItems: 1

    description:

    description:

      The physical base address and size of full the CPSW2G NUSS IO range

      The physical base address and size of full the CPSWxG NUSS IO range





  reg-names:

  reg-names:

    items:

    items:
@@ -66,12 +72,16 @@ properties: 
  dma-coherent: true

  dma-coherent: true





  clocks:

  clocks:

    description: CPSW2G NUSS functional clock

    description: CPSWxG NUSS functional clock





  clock-names:

  clock-names:

    items:

    items:

      - const: fck

      - const: fck





  assigned-clock-parents: true



  assigned-clocks: true



  power-domains:

  power-domains:

    maxItems: 1

    maxItems: 1
@@ -99,16 +109,16 @@ properties: 
        const: 0

        const: 0





    patternProperties:

    patternProperties:

      port@1:

      port@[1-2]:

        type: object

        type: object

        description: CPSW2G NUSS external ports

        description: CPSWxG NUSS external ports





        $ref: ethernet-controller.yaml#

        $ref: ethernet-controller.yaml#





        properties:

        properties:

          reg:

          reg:

            items:

            minimum: 1

              - const: 1

            maximum: 2

            description: CPSW port number

            description: CPSW port number





          phys:

          phys: