Commit 1a687574 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: restyle display clock calls part 1 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 00d64d28

drivers/gpu/drm/amd/display/dc/core/dc.c

+3 −1
Original line number Diff line number Diff line
@@ -1224,7 +1224,9 @@ bool dc_pre_update_surfaces_to_target( 
	if (prev_disp_clk < context->bw_results.dispclk_khz) {

		pplib_apply_display_requirements(core_dc, context,

						&context->pp_display_cfg);

		core_dc->hwss.set_display_clock(context);

		context->res_ctx.pool->display_clock->funcs->set_clock(

				context->res_ctx.pool->display_clock,

				context->bw_results.dispclk_khz * 115 / 100);

		core_dc->current_context->bw_results.dispclk_khz =

				context->bw_results.dispclk_khz;

	}

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -984,7 +984,7 @@ static bool construct( 
			dce110_resource_convert_clock_state_pp_to_dc(

					static_clk_info.max_clocks_state);



		dal_display_clock_store_max_clocks_state(

		pool->base.display_clock->funcs->store_max_clocks_state(

				pool->base.display_clock, max_clocks_state);

	}

	{

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+9 −39
Original line number Diff line number Diff line
@@ -497,7 +497,7 @@ static void build_audio_output( 
	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

		audio_output->pll_info.dp_dto_source_clock_in_khz =

			dal_display_clock_get_dp_ref_clk_frequency(

				pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(

						pipe_ctx->dis_clk);

	}
@@ -788,39 +788,6 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) 
	bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);

}



/**

 * Call display_engine_clock_dce80 to perform the Dclk programming.

 */

void dce110_set_display_clock(struct validate_context *context)

{

	/* Program the display engine clock.

	 * Check DFS bypass mode support or not. DFSbypass feature is only when

	 * BIOS GPU info table reports support. */



	if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {

		/*TODO: set_display_clock_dfs_bypass(

				hws,

				path_set,

				context->res_ctx.pool->display_clock,

				context->res_ctx.min_clocks.min_dclk_khz);*/

	} else {

		/*

		 * TODO: need to either port work around from DAL2 function

		 * getActualRequiredDisplayClock or program displayclock without

		 * calling vbios. Currently temporily work

		 * around by increasing the displclk by 15 percent

		 */

		dal_display_clock_set_clock(

				context->res_ctx.pool->display_clock,

				context->bw_results.dispclk_khz * 115 / 100);

	}





	/* TODO: When changing display engine clock, DMCU WaitLoop must be

	 * reconfigured in order to maintain the same delays within DMCU

	 * programming sequences. */

}



static uint32_t compute_pstate_blackout_duration(

	struct bw_fixed blackout_duration,

	const struct core_stream *stream)
@@ -1268,7 +1235,9 @@ enum dc_status dce110_apply_ctx_to_hw( 


	if (context->bw_results.dispclk_khz

			> dc->current_context->bw_results.dispclk_khz)

		dc->hwss.set_display_clock(context);

		context->res_ctx.pool->display_clock->funcs->set_clock(

				context->res_ctx.pool->display_clock,

				context->bw_results.dispclk_khz * 115 / 100);



	for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {

		struct pipe_ctx *pipe_ctx_old =
@@ -1738,7 +1707,9 @@ static void dce110_set_bandwidth(struct core_dc *dc) 
		program_wm_for_pipe(dc, pipe_ctx, dc->current_context);

	}



	dc->hwss.set_display_clock(dc->current_context);

	dc->current_context->res_ctx.pool->display_clock->funcs->set_clock(

			dc->current_context->res_ctx.pool->display_clock,

			dc->current_context->bw_results.dispclk_khz * 115 / 100);

}



static void dce110_program_front_end_for_pipe(
@@ -1959,7 +1930,6 @@ static const struct hw_sequencer_funcs dce110_funcs = { 
	.enable_display_power_gating = dce110_enable_display_power_gating,

	.power_down_front_end = dce110_power_down_fe,

	.pipe_control_lock = dce_pipe_control_lock,

	.set_display_clock = dce110_set_display_clock,

	.set_displaymarks = dce110_set_displaymarks,

	.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,

	.set_bandwidth = dce110_set_bandwidth,

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1315,7 +1315,7 @@ static bool construct( 
			dce110_resource_convert_clock_state_pp_to_dc(

					static_clk_info.max_clocks_state);



		dal_display_clock_store_max_clocks_state(

		pool->base.display_clock->funcs->store_max_clocks_state(

				pool->base.display_clock, max_clocks_state);

	}

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1315,7 +1315,7 @@ static bool construct( 
			dce110_resource_convert_clock_state_pp_to_dc(

					static_clk_info.max_clocks_state);



		dal_display_clock_store_max_clocks_state(

		pool->base.display_clock->funcs->store_max_clocks_state(

				pool->base.display_clock, max_clocks_state);

	}