Commit 1aa2a9f2 authored by Biju Das's avatar Biju Das Committed by Stephen Boyd
Browse files

dt-bindings: clock: versaclock3: Add description for #clock-cells property 



Add description for "#clock-cells" property to map indexes to the clock
output in the Table 3. ("Output Source") in the 5P35023 datasheet
(ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}. Also update the "assigned-clock-rates"
in the example.

While at it, replace clocks phandle in the example from x1_x2->x1 as
X2 is a different 32768 kHz crystal.

Suggested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230824104812.147775-2-biju.das.jz@bp.renesas.com


Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 0bb80ecc

Documentation/devicetree/bindings/clock/renesas,5p35023.yaml

+7 −4
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ properties: 
    maxItems: 1



  '#clock-cells':

    description:

      The index in the assigned-clocks is mapped to the output clock as below

      0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.

    const: 1



  clocks:
@@ -68,7 +71,7 @@ examples: 
            reg = <0x68>;

            #clock-cells = <1>;



            clocks = <&x1_x2>;

            clocks = <&x1>;



            renesas,settings = [

                80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
@@ -79,8 +82,8 @@ examples: 
            assigned-clocks = <&versa3 0>, <&versa3 1>,

                              <&versa3 2>, <&versa3 3>,

                              <&versa3 4>, <&versa3 5>;

            assigned-clock-rates = <12288000>, <25000000>,

                                   <12000000>, <11289600>,

                                   <11289600>, <24000000>;

            assigned-clock-rates = <24000000>, <11289600>,

                                   <11289600>, <12000000>,

                                   <25000000>, <12288000>;

        };

    };