Commit 1c5a2fa9 authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher
Browse files

drm/amd/display: Use correct DTO_SRC_SEL for 128b/132b encoding 



[WHY]
DP DTO isn't used for 128b/132b encoding

[HOW]
Check current link rate to determine whether using 8b/10b or 128/132b encoding

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cb849b4d

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -7064,6 +7064,7 @@ void dp_enable_link_phy( 
				pipes[i].clock_source->funcs->program_pix_clk(

				pipes[i].clock_source->funcs->program_pix_clk(

							pipes[i].clock_source,

							pipes[i].clock_source,

							&pipes[i].stream_res.pix_clk_params,

							&pipes[i].stream_res.pix_clk_params,

							dp_get_link_encoding_format(link_settings),

							&pipes[i].pll_settings);

							&pipes[i].pll_settings);

			}

			}

		}

		}

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+15 −5
Original line number Original line Diff line number Diff line
@@ -838,6 +838,7 @@ static void dce112_program_pixel_clk_resync( 
static bool dce110_program_pix_clk(

static bool dce110_program_pix_clk(

		struct clock_source *clock_source,

		struct clock_source *clock_source,

		struct pixel_clk_params *pix_clk_params,

		struct pixel_clk_params *pix_clk_params,

		enum dp_link_encoding encoding,

		struct pll_settings *pll_settings)

		struct pll_settings *pll_settings)

{

{

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -911,6 +912,7 @@ static bool dce110_program_pix_clk( 
static bool dce112_program_pix_clk(

static bool dce112_program_pix_clk(

		struct clock_source *clock_source,

		struct clock_source *clock_source,

		struct pixel_clk_params *pix_clk_params,

		struct pixel_clk_params *pix_clk_params,

		enum dp_link_encoding encoding,

		struct pll_settings *pll_settings)

		struct pll_settings *pll_settings)

{

{

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -970,6 +972,7 @@ static bool dce112_program_pix_clk( 
static bool dcn31_program_pix_clk(

static bool dcn31_program_pix_clk(

		struct clock_source *clock_source,

		struct clock_source *clock_source,

		struct pixel_clk_params *pix_clk_params,

		struct pixel_clk_params *pix_clk_params,

		enum dp_link_encoding encoding,

		struct pll_settings *pll_settings)

		struct pll_settings *pll_settings)

{

{

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -993,6 +996,11 @@ static bool dcn31_program_pix_clk( 
#if defined(CONFIG_DRM_AMD_DC_DCN)

#if defined(CONFIG_DRM_AMD_DC_DCN)

		/* Enable DTO */

		/* Enable DTO */

		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)

		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)

			if (encoding == DP_128b_132b_ENCODING)

				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

						DP_DTO0_ENABLE, 1,

						PIPE0_DTO_SRC_SEL, 2);

			else

				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],

						DP_DTO0_ENABLE, 1,

						DP_DTO0_ENABLE, 1,

						PIPE0_DTO_SRC_SEL, 1);

						PIPE0_DTO_SRC_SEL, 1);
@@ -1198,12 +1206,13 @@ const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 
static bool dcn20_program_pix_clk(

static bool dcn20_program_pix_clk(

		struct clock_source *clock_source,

		struct clock_source *clock_source,

		struct pixel_clk_params *pix_clk_params,

		struct pixel_clk_params *pix_clk_params,

		enum dp_link_encoding encoding,

		struct pll_settings *pll_settings)

		struct pll_settings *pll_settings)

{

{

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;





	dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);

	dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);





	if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&

	if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&

			clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {

			clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
@@ -1243,6 +1252,7 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = { 
static bool dcn3_program_pix_clk(

static bool dcn3_program_pix_clk(

		struct clock_source *clock_source,

		struct clock_source *clock_source,

		struct pixel_clk_params *pix_clk_params,

		struct pixel_clk_params *pix_clk_params,

		enum dp_link_encoding encoding,

		struct pll_settings *pll_settings)

		struct pll_settings *pll_settings)

{

{

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -1265,7 +1275,7 @@ static bool dcn3_program_pix_clk( 
		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

	} else

	} else

		// For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table

		// For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table

		dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);

		dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);





	return true;

	return true;

}

}

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1435,6 +1435,7 @@ static enum dc_status dce110_enable_stream_timing( 
		if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

		if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

				pipe_ctx->clock_source,

				pipe_ctx->clock_source,

				&pipe_ctx->stream_res.pix_clk_params,

				&pipe_ctx->stream_res.pix_clk_params,

				dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),

				&pipe_ctx->pll_settings)) {

				&pipe_ctx->pll_settings)) {

			BREAK_TO_DEBUGGER();

			BREAK_TO_DEBUGGER();

			return DC_ERROR_UNEXPECTED;

			return DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -892,6 +892,7 @@ enum dc_status dcn10_enable_stream_timing( 
	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

			pipe_ctx->clock_source,

			pipe_ctx->clock_source,

			&pipe_ctx->stream_res.pix_clk_params,

			&pipe_ctx->stream_res.pix_clk_params,

			dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),

			&pipe_ctx->pll_settings)) {

			&pipe_ctx->pll_settings)) {

		BREAK_TO_DEBUGGER();

		BREAK_TO_DEBUGGER();

		return DC_ERROR_UNEXPECTED;

		return DC_ERROR_UNEXPECTED;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -700,6 +700,7 @@ enum dc_status dcn20_enable_stream_timing( 
	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

			pipe_ctx->clock_source,

			pipe_ctx->clock_source,

			&pipe_ctx->stream_res.pix_clk_params,

			&pipe_ctx->stream_res.pix_clk_params,

			dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings),

			&pipe_ctx->pll_settings)) {

			&pipe_ctx->pll_settings)) {

		BREAK_TO_DEBUGGER();

		BREAK_TO_DEBUGGER();

		return DC_ERROR_UNEXPECTED;

		return DC_ERROR_UNEXPECTED;