Commit 1dbcf770 authored by Jiadong Zhu's avatar Jiadong Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: Reset CP_VMID_PREEMPT after trailing fence signaled 



When MEC executes unmap_queue for mid command buffer preemption, it will
kick the write pointer of the gfx ring, set CP_VMID_PREEMPT to trigger the
preemption and wait for CP_VMID_PREEMPT becomes zero after the preemption
done. There is a race condition that PFP may excute the resetting command
before MEC set CP_VMID_PREEMPT. As a result, hang happens as
CP_VMID_PREEMPT is always 0xffff.

To avoid this, we send resetting CP_VMID_PREEMPT command after the trailing
fence is siganled and update gfx write pointer explicitly.

Signed-off-by: default avatarJiadong Zhu <Jiadong.Zhu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.3.x
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2535
parent 858fd168

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+4 −4
Original line number Diff line number Diff line
@@ -5369,10 +5369,6 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) 
	amdgpu_ring_alloc(ring, 13);

	gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,

				 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT);

	/*reset the CP_VMID_PREEMPT after trailing fence*/

	amdgpu_ring_emit_wreg(ring,

			      SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),

			      0x0);



	/* assert IB preemption, emit the trailing fence */

	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
@@ -5395,6 +5391,10 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) 
		DRM_WARN("ring %d timeout to preempt ib\n", ring->idx);

	}



	/*reset the CP_VMID_PREEMPT after trailing fence*/

	amdgpu_ring_emit_wreg(ring,

			      SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),

			      0x0);

	amdgpu_ring_commit(ring);



	/* deassert preemption condition */