Commit 1de76941 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
Browse files

media: atomisp: drop ia_css_pipe_update_qos_ext_mapped_arg 



This function is not used. Drop it.

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 6a28541f

drivers/staging/media/atomisp/pci/ia_css_pipe_public.h

+0 −23
Original line number Diff line number Diff line
@@ -479,29 +479,6 @@ ia_css_pipe_get_qos_ext_state(struct ia_css_pipe *pipe, 
			      u32 fw_handle,

			      bool *enable);



/* ISP2401  */

/* @brief  Update mapped CSS and ISP arguments for QoS pipe during SP runtime.

 * @param[in] pipe	Pipe handle.

 * @param[in] fw_handle	Extension firmware Handle (ia_css_fw_info.handle).

 * @param[in] css_seg	Parameter memory descriptors for CSS segments.

 * @param[in] isp_seg	Parameter memory descriptors for ISP segments.

 *

 * @return

 * 0			: Success

 * -EINVAL		: Invalid Parameters

 * -EBUSY	: Inactive QOS Pipe

 *					(No active stream with this pipe)

 *

 * \deprecated{This interface is used to temporarily support a late-developed,

 * specific use-case on a specific IPU2 platform. It will not be supported or

 * maintained on IPU3 or further.}

 */

int

ia_css_pipe_update_qos_ext_mapped_arg(struct ia_css_pipe *pipe,

				      u32 fw_handle,

				      struct ia_css_isp_param_css_segments *css_seg,

				      struct ia_css_isp_param_isp_segments *isp_seg);



/* @brief Get selected configuration settings

 * @param[in]	pipe	The pipe.

 * @param[out]	config	Configuration settings.

drivers/staging/media/atomisp/pci/sh_css.c

+0 −82
Original line number Diff line number Diff line
@@ -10089,88 +10089,6 @@ ia_css_pipe_get_qos_ext_state(struct ia_css_pipe *pipe, uint32_t fw_handle, 
	return err;

}



/* ISP2401 */

int

ia_css_pipe_update_qos_ext_mapped_arg(struct ia_css_pipe *pipe,

				      u32 fw_handle,

				      struct ia_css_isp_param_css_segments *css_seg,

				      struct ia_css_isp_param_isp_segments *isp_seg)

{

	unsigned int HIVE_ADDR_sp_group;

	static struct sh_css_sp_group sp_group;

	static struct sh_css_sp_stage sp_stage;

	static struct sh_css_isp_stage isp_stage;

	const struct ia_css_fw_info *fw;

	unsigned int thread_id;

	struct ia_css_pipeline_stage *stage;

	int err = 0;

	int stage_num = 0;

	enum ia_css_isp_memories mem;

	bool enabled;



	IA_CSS_ENTER("");



	fw = &sh_css_sp_fw;



	/* Parameter Check */

	if (!pipe || !pipe->stream) {

		IA_CSS_ERROR("Invalid Pipe.");

		err = -EINVAL;

	} else if (!(pipe->config.acc_extension)) {

		IA_CSS_ERROR("Invalid Pipe (No Extension Firmware).");

		err = -EINVAL;

	} else if (!sh_css_sp_is_running()) {

		IA_CSS_ERROR("Leaving: queue unavailable.");

		err = -EBUSY;

	} else {

		/* Query the thread_id and stage_num corresponding to the Extension firmware */

		ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id);

		err = ia_css_pipeline_get_stage_from_fw(&pipe->pipeline, fw_handle, &stage);

		if (!err) {

			/* Get the Extension State */

			enabled = (SH_CSS_QOS_STAGE_IS_ENABLED(&sh_css_sp_group.pipe[thread_id],

							       stage->stage_num)) ? true : false;

			/* Update mapped arg only when extension stage is not enabled */

			if (enabled) {

				IA_CSS_ERROR("Leaving: cannot update when stage is enabled.");

				err = -EBUSY;

			} else {

				stage_num = stage->stage_num;



				HIVE_ADDR_sp_group = fw->info.sp.group;

				sp_dmem_load(SP0_ID,

					     (unsigned int)sp_address_of(sp_group),

					     &sp_group,

					     sizeof(struct sh_css_sp_group));

				hmm_load(sp_group.pipe[thread_id].sp_stage_addr[stage_num],

					 &sp_stage, sizeof(struct sh_css_sp_stage));



				hmm_load(sp_stage.isp_stage_addr,

					 &isp_stage, sizeof(struct sh_css_isp_stage));



				for (mem = 0; mem < N_IA_CSS_ISP_MEMORIES; mem++) {

					isp_stage.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].address =

					    css_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].address;

					isp_stage.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].size =

					    css_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].size;

					isp_stage.binary_info.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].address

					    =

						isp_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].address;

					isp_stage.binary_info.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].size

					    =

						isp_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].size;

				}



				hmm_store(sp_stage.isp_stage_addr,

					  &isp_stage,

					  sizeof(struct sh_css_isp_stage));

			}

		}

	}

	IA_CSS_LEAVE("err:%d handle:%u", err, fw_handle);

	return err;

}



static void

sh_css_hmm_buffer_record_init(void)

{