Commit 1ecf3dcb authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Standardise naming for ID_PFR2_EL1 



To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_PFR2_EL1 register have an _EL1 suffix.

No functional change.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-11-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 0a648056

arch/arm64/include/asm/sysreg.h

+2 −2
Original line number Diff line number Diff line
@@ -768,8 +768,8 @@ 
#define ID_DFR0_COPSDBG_SHIFT		4

#define ID_DFR0_COPDBG_SHIFT		0



#define ID_PFR2_SSBS_SHIFT		4

#define ID_PFR2_CSV3_SHIFT		0

#define ID_PFR2_EL1_SSBS_SHIFT		4

#define ID_PFR2_EL1_CSV3_SHIFT		0



#define MVFR0_FPROUND_SHIFT		28

#define MVFR0_FPSHVEC_SHIFT		24

arch/arm64/kernel/cpufeature.c

+2 −2
Original line number Diff line number Diff line
@@ -560,8 +560,8 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = { 
};



static const struct arm64_ftr_bits ftr_id_pfr2[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),

	ARM64_FTR_END,

};