Commit 1f5dcb73 authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher
Browse files

drm/amd/display: Fix dpstreamclk programming 



[WHY]
Currently programming incorrect hpo inst as well as selecting incorrect source

[HOW]
Use hpo inst instead of otg inst to select dpstreamclk inst

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b5e924bd

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

+5 −3
Original line number Diff line number Diff line
@@ -158,9 +158,11 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) 
	}

}



void dccg31_set_dpstreamclk(struct dccg *dccg,

void dccg31_set_dpstreamclk(

		struct dccg *dccg,

		enum streamclk_source src,

			    int otg_inst)

		int otg_inst,

		int dp_hpo_inst)

{

	if (src == REFCLK)

		dccg31_disable_dpstreamclk(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h

+2 −6
Original line number Diff line number Diff line
@@ -161,11 +161,6 @@ struct dccg *dccg31_create( 


void dccg31_init(struct dccg *dccg);



void dccg31_set_dpstreamclk(

		struct dccg *dccg,

		enum streamclk_source src,

		int otg_inst);



void dccg31_enable_symclk32_se(

		struct dccg *dccg,

		int hpo_se_inst,
@@ -207,7 +202,8 @@ void dccg31_get_dccg_ref_freq( 
void dccg31_set_dpstreamclk(

	struct dccg *dccg,

	enum streamclk_source src,

	int otg_inst);

	int otg_inst,

	int dp_hpo_inst);



void dccg31_set_dtbclk_dto(

		struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

+7 −6
Original line number Diff line number Diff line
@@ -184,7 +184,8 @@ void dccg314_set_dtbclk_dto( 
void dccg314_set_dpstreamclk(

		struct dccg *dccg,

		enum streamclk_source src,

		int otg_inst)

		int otg_inst,

		int dp_hpo_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -192,26 +193,26 @@ void dccg314_set_dpstreamclk( 
	dccg314_set_dtbclk_p_src(dccg, src, otg_inst);



	/* enabled to select one of the DTBCLKs for pipe */

	switch (otg_inst) {

	switch (dp_hpo_inst) {

	case 0:

		REG_UPDATE_2(DPSTREAMCLK_CNTL,

					DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1,

					DPSTREAMCLK0_SRC_SEL, 0);

					DPSTREAMCLK0_SRC_SEL, otg_inst);

		break;

	case 1:

		REG_UPDATE_2(DPSTREAMCLK_CNTL,

					DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1,

					DPSTREAMCLK1_SRC_SEL, 1);

					DPSTREAMCLK1_SRC_SEL, otg_inst);

		break;

	case 2:

		REG_UPDATE_2(DPSTREAMCLK_CNTL,

					DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1,

					DPSTREAMCLK2_SRC_SEL, 2);

					DPSTREAMCLK2_SRC_SEL, otg_inst);

		break;

	case 3:

		REG_UPDATE_2(DPSTREAMCLK_CNTL,

					DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1,

					DPSTREAMCLK3_SRC_SEL, 3);

					DPSTREAMCLK3_SRC_SEL, otg_inst);

		break;

	default:

		BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c

+2 −1
Original line number Diff line number Diff line
@@ -211,7 +211,8 @@ static void dccg32_get_dccg_ref_freq(struct dccg *dccg, 
void dccg32_set_dpstreamclk(

		struct dccg *dccg,

		enum streamclk_source src,

		int otg_inst)

		int otg_inst,

		int dp_hpo_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+2 −1
Original line number Diff line number Diff line
@@ -101,7 +101,8 @@ struct dccg_funcs { 
	void (*set_dpstreamclk)(

			struct dccg *dccg,

			enum streamclk_source src,

			int otg_inst);

			int otg_inst,

			int dp_hpo_inst);



	void (*enable_symclk32_se)(

			struct dccg *dccg,