Commit 1f5e9283 authored by Matthias Kaehlcke's avatar Matthias Kaehlcke Committed by Heiko Stuebner
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ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger 



The flash write protect pin is currently named 'FW_WP_AP', which is
how the signal is called in the schematics. The Chrome OS ABI
requires the pin to be named 'AP_FLASH_WP_L', which is also how
it is called on all other veyron devices. Rename the pin to match
the ABI.

Signed-off-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200106135142.1.I3f99ac8399a564c88ff48ae6290cc691b47c16ae@changeid


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent e964d463

arch/arm/boot/dts/rk3288-veyron-fievel.dts

+5 −1
Original line number Diff line number Diff line
@@ -380,7 +380,11 @@ &gpio7 { 
			  "PWR_LED1",

			  "TPM_INT_H",

			  "SPK_ON",

			  "FW_WP_AP",

			  /*

			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call

			   * it FW_WP_AP.

			   */

			  "AP_FLASH_WP_L",

			  "",



			  "CPU_NMI",